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Dom_123

basys 3 WiFi usage

Question

Hi @jpeyron,

I am also attempting to send Pmod Hygro data to a PC (or to the cloud) using the Pmod WiFi. Do I need an SD card for this to be possible (like in the tutorial) or is there another way. I'm using the BASYS 3 FPGA

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Hi @Dom_123,

Welcome to the Digilent Forums!

I split this thread and started a new topic since its with a different board. This sounds like an interesting project.

You will need to use an SD card reader something like the Pmod MicroSD to use the HTTPServer example for the Pmod WIFI IP Core.

You should not need an SD card for the other Pmod WIFI IP Core examples.

best regards,

Jon

 

 

 

 

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Thanks for the quick reply! @jpeyron,

Where can I find the Pmod WiFi IP Core examples? Also, in regards to the Pmod Hygro, using the example provided doesn't appear to generate actual temperature and humidity data. The example instead prints a range of readings to the serial term and doesn't use the sensor itself at all by the looks of things. Any help with collecting actual humidity and temperature data would also be greatly appreciated!

Thanks,

Dom.

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Hi @Dom_123,

1) Are you talking about the Pmod HYGRO IP core example here?

2) Please provide a screen shot of the serial terminal output, Vivado block design as well as your wrapper, xdc and SDK code.

3) The Pmod WIFI IP and Pmod HYGRO IP Core and can be found in the Vivado library.  Here is the Getting Started with Digilent Pmod IPs tutorial. Make sure that you have installed the digilent board files as described here

4) What version of Vivado are you using?

best regards,

Jon

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Hello again, 

I am talking about that example yes. I have attached the SDK code and a screenshot of terminal and block design.

Sorry for the miss communication earlier. I have been trying to implement the Pmod HYGRO and Pmod WiFi IP's for some time. and have used the getting started tutorial to do so.

I am running vivado 2018.3, is that version 'too new'? 

Thanks again,

Dom. 

teraterm SC.jpg

example for guy.rtf HYGRO_JBport.pdf

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Hi @Dom_123,

I was able to verify a Vivado 2018.2 Basys 3 Pmod HYGRO project here.  I have attached a screen shot of the tera term output which is updating/changing. Please download this project and see if you get the expected results.

best regards,

Jon

basys3_Pmod_HYGRO.jpg

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Hi @jpeyron,

When attempting to run this file I get an (as shown in the picture) to do with the IP's. Is this because my IP files are out of date? where did you locate the IP files for this model?

thanks again,

Dom. 

IP upgrad needed pic.jpg

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These are the errors that show when i open the block design (see picture). Also, in the design it states that the JA pmod port isnt connected and doesnt allow me to connect and if i ignore such errors and continue to SDK then the tera term window again shows random variables for temperature and humidity. 

Errors for jo.jpg

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@jpeyron

These are the tera term readings i get from your example which are similar to the ones i was getting when i configured this example. Will it be anything to do with the way my Basys 3 board is configured physically? Thanks again.

Dom.

readings from jos example (basys).jpg

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Hi @Dom_123,

1) I miss read your vivado version. Sorry for the confusion this may have caused. Here is a verified Pmod HYGRO Basys 3 Vivado 2018.3 project.  After downloading and  loading the linked project in Vivado 2018.3, click into the project settings and update the IP repository to reflect the path to your vivado library folder. 

2) What Pmod WIFI example are you trying to run?

best regards,

Jon

Basys3_Hygro.jpg

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Hi @jpeyron,

No worries, thank you for your continued support ill try running that now.

Just trying to run a basic Wi-Fi scan example to make sure the Wi-Fi module is connected and working as it should for now before digging any further. 

thanks again,

Dom. 

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Hi @jpeyron,

Unfortunately this also appears not to work as i receive errors with the block design, are my Vivado ip library's out of date perhaps? could you send me the correct ones if you have them as the ones shown are the latest i can find. (Pictures below).632112421_errors2.thumb.jpg.751580f52c0cdf6aa06e6e21034d65ba.jpg

Dom. 

issues with new build.jpg

library version proof.png

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Hi @jpeyron

I believe my issues to be hardware based and I have attached a photo of the way my board is setup. I believe this because even without the HYGRO connected my serial print values are the same random ones.

Let me know what you think, thanks again.

Dom.

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1 minute ago, Dom_123 said:

Hi @jpeyron

I believe my issues to be hardware based and I have attached a photo of the way my board is setup. I believe this because even without the HYGRO connected my serial print values are the same random ones.

Let me know what you think, thanks again.

Dom.

55455455_303803353643936_6578804189869113344_n.thumb.jpg.17e8ef702fb7df99ebe1799f0894f2f2.jpg

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Hi @Dom_123,

 

Looking at your previous errors. Vivado is not able to find the port information. This is usually due to either board files and or the Vivado-library being installed incorrectly or the paths to these folders in the project are wrong.  

The Vivado-library can be downloaded from here. Please unzip and place  the unzipped folder in a different folder  other than downloads. I typically use either my desktop or documents folder. When attaching the IP repository include the whole Vivado-library folder. 

First download the board files from here. The board files can be installed two different ways for Vivado 2018.3.

1) In the tutorial the "Vivado_init.tcl"  file is opened in the “utility” subdirectory of the vivado-boards repo. This file is a script that will be run whenever Vivado is launched. It will load Digilent's board files for use in Vivado from the directory they were extracted into. Change the text “<extracted path>” in the script to the extracted location of vivado-boards. Save and close the file.

2) Install the contents of the digilent board file folder "vivado-boards/new/board_files/" directly in the board file folder here: C:\Xilinx\Vivado\2018.3\data\boards\board_files

When creating a new project are you able to select the basys 3 board and create a block design with the board tab available? 

Please attach a screen shot of this. 

 

best regards,

Jon

 

 

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Hi @Dom_123,

Lets first get the Pmod HYGRO working on your Basys 3 with Vivado 2018.3.

The steps to create a Basys 3/Pmod Hygro / Vivado 2018.3 project are as follows.

1) Create a project selecting the Basys 3.

2) Add the full Vivado-library folder to the IP repository. Select project settings->ip->repository and select the path to the unzipped Vivado library folder on your PC.

3) Create a block design.

4) Select tab and drag the clock on to the block design. Open clocking wizard and select reset for the ext_reset_in then hit ok.

5) Add Microblaze IP Core

6) Drag usb from the board tab and add it to the block design. Then right click on either JA, JB,JC and select Pmod HYGRO. 

7) Run block automation. for local memory select 128 KB everything else level at default settings.

8). Now run connection automation select all and click OK.

9) Re-generate layout and validate the block design.

10) Create a wrapper by clicking sources and right clicking on the block design.

11) Generate a bitstream. export hardware including the bitstream and launch SDK.

12) Once SDK is launched add a new application. Choose whatever name you would like but do not include spaces. keep all the other default settings and hit next.

13) Select empty template and click finish.

14) Open the vivado library folder on your pc to here:  \vivado-library\ip\Pmods\PmodHYGRO_v1_0\drivers\PmodHYGRO_v1_0\examples and drag the main.c to the src folder in the empty application. 

15) Connect and turn on your basys 3 to your PC and the Pmod HYGRO to the Pmod Port you selected in your block design I.E. JA,JB or JC.

16) On your PC open a serial terminal emulator like tera term and connect the comport of the Basys 3. The baud rate should be 9600 and everything else is typically left at default setting.

17) Next in SDK program the FPGA and run as->launch on hardware(system debugger).

18) You should be getting real data outputted to the serial emulator from the Basys 3.

19) Are you getting expected data?

best regards,

Jon  

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I followed the above instructions and unfortunately the results are the same set of random variables. I have attached screenshots as proof of this.

I will continue to trouble-shoot in the meantime.

Thanks.

Dom. 

failed results new.png

library version proof.png

validated.jpg

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Just now, Dom_123 said:

I followed the above instructions and unfortunately the results are the same set of random variables. I have attached screenshots as proof of this.

I will continue to trouble-shoot in the meantime.

Thanks.

Dom. 

failed results new.png

library version proof.png

validated.jpg

**** Wrong library proof file.... should be this SC instead. 

Dom.

basys 3 proof.jpg

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Hi @Dom_123,

1) Please attach a screen shot of your current Vivado block design and your wrapper and SDK file.

2) Please attach a picture of your board/Pmod HYGRO set up. 

3) Are you changing any of the Microblaze setting besides setting the Local memory to 128 KB?

best regards,

Jon

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Hi @jpeyron,

I am not changing any of the other MicroBlaze IP settings no, aside from local memory to 128kb. Also the SDK file is to large to share even when zipped. how else can i share this file with you? Other files/pictures are below

Thanks,

Dom.

 

55500770_626011927824042_5832855073058717696_n.jpg

sc of block design.jpg

design_1_wrapper.v

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Hi @Dom_123,

Sorry for the confusion I am looking for the main.c in the SDK file.

1) Also can you attach a screen shot of the SDK project explore section.

2) In one of your screen shots I see 2 different HW_Platforms in the project explore section.

And in another screen shot I see a bsp's without a corresponding application. 

3) When you program the fpga are you using the default settings?

4) To run the application are right clicking on the application and selecting run as->launch on hardware(system debugger)?

5) are you changing any of the setting in SDK?

best regards,

Jon

 

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@jpeyron,

The Main.c file used is the exact same file provided in the example with absolutely no changes. I am using default programming settings when i program the FPGA. I am also using the run as launch on hardware (system debugger). I am not changing any of the SDK settings. I am using windows 10, will that make any difference? I have attached a screenshot of the project explore window. 

thanks,

Dom.

 

Picture for jo of project e.png

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Hi @Dom_123,

I see your problem. You have multiple design_1_wrapper_hw_platforms. My guess is that your application is using the original hw_platform and that is why you keep getting the same data. All of your changes are not being implemented.

One way to get multiple platforms is to not start with fresh SDK folder but rather just change the existing vivado hardware and then import the changed hardware platform without deleting the previous SDK folder. 

The easiest way to fix this is to click into the project folder and delete the .sdk folder. Then in Vivado 2018.3 re-export the hardware and launch sdk.

Then create a new application and add the main.c from the example folder in the Pmod HYGRO IP Core to the scr folder in the application. Then program the FPGA and right click on the application selecting run as->launch oun hardware(system debugger).

best regards,

Jon

Basys3_Hygro_1.jpg

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Hi @Dom_123,

Also looking at your picture setup, I also noticed that you left the mode jumper (JP1) floating. The mode jumper (JP1) is on the top right  of the Basys 3 close to Pmod Port JB where you have the Pmod HYGRO connected. You need to set the mode to JTAG using a jumper on the two middle pins or shorting the middle two pins together with metal wire before programming the FPGA and running the SDK Application.

best regards,

Jon

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