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Posted (edited)

Hey,

Can I use Digilent's peripheral "Pmod DA2: Two 12-bit D/A Outputs" on zedboard ? 

If I check,  https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start this link, under Platforms Supported, ZedBoard is not listed. That makes me wonder if I still can use PMODDA2 and other Pmods on my zedboard? 

IF yes, i think we do not have an IP specificially created for PMODDA2... 

Edited by mehmetdemirtas89

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Posted (edited)

Hello @mehmetdemirtas89,

Yes, you can use the PmodDA2 with the zedboard.

Note that there is no IP core in Digilent's vivado_library for the DA2. However, on the reference page for the DA2, you can find usage information.

You can download the verilog example and the reference component. You will need to retarget the example project to use the zedboard instead of an Artix based board. You will also have to supply a constraints file for the project.

Here is the physical setup I tested. (My zedboad's jtag usb connector broke off a while back so I have to use the Xilinx platform cable to program)

image.thumb.png.18d85ca94cf0499a81c3eb49eff7fedc.png

Here is what the logic analyzer shows while it is running

image.thumb.png.36a7c533105b5e13532a2d54c0fee357.png

And zoomed so you can see the writes

image.thumb.png.8089a377450fe2fd80c7d08da219f404.png

Edited by kwilber

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19 hours ago, kwilber said:

Hello @mehmetdemirtas89,

Yes, you can use the PmodDA2 with the zedboard.

Note that there is no IP core in Digilent's vivado_library for the DA2. However, on the reference page for the DA2, you can find usage information.

You can download the verilog example and the reference component. You will need to retarget the example project to use the zedboard instead of an Artix based board. You will also have to supply a constraints file for the project.

Here is the physical setup I tested. (My zedboad's jtag usb connector broke off a while back so I have to use the Xilinx platform cable to program)

image.thumb.png.18d85ca94cf0499a81c3eb49eff7fedc.png

Here is what the logic analyzer shows while it is running

image.thumb.png.36a7c533105b5e13532a2d54c0fee357.png

And zoomed so you can see the writes

image.thumb.png.8089a377450fe2fd80c7d08da219f404.png

hey  kwilber,

thank you for your helpful response. When i open the example project pmod_da2_demo.xpr, there is a "non-module file" DA2RefComp.vhd. When I put this .vhd file to the / Pmod_DA2_Demo\Pmod_DA2_Demo.srcs\sources_1\new, this demo project still do not work.  Should I create an IP from DA2RefComp.vhd to make this demo work? 

have a nice day,

 

 2089553847_EkranAlnts.JPG.5f2d9d0db324a740025881c936c36dd2.JPG

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You can delete the reference to DA2RefComp.vhd under non-module files (right click on the file and select "Remove file from project"). Then re-add the file to the project using the "Add sources" command. Simply copying the file to the directory from outside of vivado is not sufficient for vivado to know about the file.

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Posted (edited)
42 minutes ago, kwilber said:

You can delete the reference to DA2RefComp.vhd under non-module files (right click on the file and select "Remove file from project"). Then re-add the file to the project using the "Add sources" command. Simply copying the file to the directory from outside of vivado is not sufficient for vivado to know about the file.

Still, the example demo project gives errors when I run Behavioral Simulation. I think @jpeyron might help because i guess he is the one created the testbench file. (Module Name:   C:/Users/jpeyron/Desktop/xilinx software and files/RefCompIssue/test_bench.v) 

I will search for the following errors from Xilinx forums:

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/mehmet/Desktop/Pmod_DA2_Demo/Pmod_DA2_Demo.sim/sim_1/behav/xsim/xvlog.log' file for more information.
 

Edited by mehmetdemirtas89

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Posted (edited)

The simulation ran without issue for me.

The error message indicates there were errors during the compile. Can you post the full output?

After you took care of the "non-module files", did you use the "Refresh hierarchy" command (right click in the sources window and select  "Refresh hierarchy").

Did you retarget the project for the Zedboard? (double click on the "Project part" link in the "Project Summary").

 

 

Edited by kwilber

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Posted (edited)

image.png.66aeb2ca5cdf11aa67c1c86b544d7999.pngimage.png.fef10843e34c7812cfdc854dee979765.png

I have done all the things you say but still get the errors. Since it is only simulation, not synthesis and implementation i didnt arrange the zedboard_master.xdc constraints.. The errors are like follows:

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/mehmet/Desktop/Pmod_DA2_Demo/Pmod_DA2_Demo.sim/sim_1/behav/xsim/xvlog.log' file for more information.

 

ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/mehmet/Desktop/Pmod_DA2_Demo/Pmod_DA2_Demo.sim/sim_1/behav/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

yes it seems like a compiation error. I use Vivado 2018.2 which runs on Windows 10 by the way. 

 

 

 

Edited by mehmetdemirtas89

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Ah thats right, I had to correct that as well. Just change the instance name of the up/down counter to counter. Sorry I forgot about that.

up_down_counter counter (
    .clk(clk_div), 
    .counter(counter1)
    );

 

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1 minute ago, kwilber said:

Ah thats right, I had to correct that as well. Just change the instance name of the up/down counter to counter. Sorry I forgot about that.


up_down_counter counter (
    .clk(clk_div), 
    .counter(counter1)
    );

 

Thank you @kwilber. It was such an easy and silly question sorry for that  : )  Now, since the simulation part is OK,  i hope i will create an IP Core for it and then make it work! thanks again...

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