Use 4x4 KeyPad using JB Pmod port of Basys3 FPGA

[MMateos]

Hello, I am designing a project in which I need to register the input from a 4x4 matrix KeyPad (this model) and to do so I have written the following VHDL test code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Display is
    Port (
        selected                : in std_logic;
        Row_Vector            : in std_logic_vector(3 downto 0);
        Col_Vector            : in std_logic_vector(3 downto 0);
        display_code          : out std_logic_vector(6 downto 0);
        display_ctrl          : out std_logic_vector(3 downto 0)
    );
end Display;

architecture Behavioral of Display is

signal Displayed : std_logic_vector(3 downto 0);

begin
                     
process(Displayed)
begin
    case Displayed is
        when "0000" => display_code <= "0000001"; -- "0"     
        when "0001" => display_code <= "1001111"; -- "1" 
        when "0010" => display_code <= "0010010"; -- "2" 
        when "0011" => display_code <= "0000110"; -- "3" 
        when "0100" => display_code <= "1001100"; -- "4" 
        when "0101" => display_code <= "0100100"; -- "5" 
        when "0110" => display_code <= "0100000"; -- "6" 
        when "0111" => display_code <= "0001111"; -- "7" 
        when "1000" => display_code <= "0000000"; -- "8"     
        when "1001" => display_code <= "0000100"; -- "9" 
        when "1010" => display_code <= "0000010"; -- a
        when "1011" => display_code <= "1100000"; -- b
        when "1100" => display_code <= "0110001"; -- C
        when "1101" => display_code <= "1000010"; -- d
        when "1110" => display_code <= "0110000"; -- E
        when "1111" => display_code <= "0111000"; -- F
        when others => display_code <= "1111111";
    end case;
end process;

process(selected,Row_Vector,Col_Vector)
begin
    
    if selected = '0' then
        Displayed <= Row_Vector;
    else
        Displayed <= Col_Vector;
    end if;
    
end process;

display_ctrl <= "1110";

end Behavioral;

I have attached all the source code for my test, which includes a button debouncer (U18 button), which I push to show the value that I read from the A14,A16,B15 and B16 pins for the rows and A15,A17,C15 and C16 for the columns of the KeyPad.

For example: when there are no cables connected to the row pins and I have not pushed the button, the value read from the row pins is shown in the 7-Segment display, which is "1111" (F). This means that when I connect a cable on any of the pins, a '0' is written at the input pin. If I connect a cable at the first row pin, the value read is "1110" and E is displayed. Following this logic, when I connect a cable to the second row pin and I leave the other ones disconnected, it should be displayed D ("1101") but instead 8 is displayed, which corresponds to "1000", which would mean that I have row 1, row 2 and row 3 cables connected, which is not the case.

What could be the problem here? My main problem is to undestand how to communicate the keypad with the Basys3 FPGA

Test_Code.zip

[kwilber]

You might want to have a look at the examples for the PmodKYPD found here. It does just about the same thing you are trying - read from the keypad and display on a 7-segment led. There are both verilog and VHDL versions.

 

[jpeyron]

Hi @MMateos,

Welcome to the Digilent Forums! We have the Pmod KYPD which has Verilog and VHDL examples using it with a Nexys 3 and ISE. Here is an unverified VHDL Basys 3_PmodKYPD Vivado 2018.2 project that should help with your project. 

cheers,

Jon

[MMateos]

Thank you for the answers!

[jpeyron]

Hi @MMateos,

I just verified the above linked project works without an issue

cheers,

Jon