FPGA board for capturing high speed ADC data

[EELE]

Hi there,

I'm a newbie here, and I'm looking for an FPGA evaluation board for capturing data from a high speed ADC (such as ADS5484EVM 16 bit, 170 Msps from Texas Instrument). I found "Nexys A7 - FPGA Trainer Board Recommended for ECE Curriculum" on Digilent's store but I don't know if it can handle this task or not.

Could anyone please confirm if I can use this development board or recommend for any other boards? Also, will I need to buy an adapter to connect to ADS5484EVM?

Any recommendation would be highly appreciate. Thank you!

[zygot]

@EELE

It's a shame but there aren't any reasonably priced options for Xilinx FPGA development board connectivity to high speed ADCs in the >12 bit > 100 MHz realm. I'm always looking out for such things. There are a few quite expensive FMC boards ( Terasic has a new FMC ADC board that might be affordable but their website doesn't post a price so I don't know if it's available or not  ). There are some options using Intel FPGA boards and HSMC connectors. Most of the high speed ADC evaluation boards from vendors like ADI or Ti require specialized data capture/control hardware and are designed to just evaluate performance. Of those few offer a wide band general purpose analog front end as they are geared toward communications applications.

For Digilent FPGA boards with an FMC connector you have to be careful because there are restrictions using IOSERDES2 and clocking options. Ideally you want data and framing clocks in the same IO bank as your LVDS data. Texas Instruments offers FMC adapter boards that might work with their ADC eval boards but these assign clock and data in a way that doesn't work with most Xilinx FPGA board FMC pin assignments. For ADCs with LVDS interfaces 2-wire options are easier to work with than 1-wire. Lastly, for 16-bit LVDS you need to use more than 1 IOSERDES2 per channel (pin). You are not going to find much assistance with master-slave 14:1 or 16:1 IOSERDES2 1-wire implementations from the FPGA vendors. Intel is the worst as they want to sell you high-end expensive silicon for advanced IO interfaces.

In general the analog front end designs that drive ADC inputs are highly specific especially for  high-speed ADC applications.

I've used the Terasic converter boards with Intel based FPGA development boards and they have a good general purpose wide-band analog support. I don't recommend products but avoid the DEV-ADC34JXX JESD204B ADC evaluation board from Ti. It's made by a third party who refuses to offer any support, or even reply to customer inquiries, so it's pretty useless except to see it work with the one configuration file provided. It uses a 4 channel ADC and 2 channels are set up for wide-band and 2 for narrow-band so it's not really good as a 4 channel ADC interface. This is not an unusual setup for eval boards.

I've learned not to buy anything until I've downloaded supporting HDL projects to verify that I can create my own application without having to buy an IP license. Building demo code in Vivado or Quartus before spending money is a very good practice in general; it's the only way to determine if the hardware is useful. If you are going to try and adapt a a vendor ADC evaluation board using an adaptor you have to trace through all of the signals to your FPGA to verify that it works.

Since I mentioned JESD204B, this is the best interface available and uses transceivers. Be careful though as no one gives away JESD204B IP so making a custom design without having a license for the FPGA vendor IP is problematic. Also, since it uses transceivers you need an MGT clock reference that fits your requirements.

Let's see... did I forget anything?  Give me a week it'll interrupt my day sooner or later...

[xc6lx45]

Before you spend money, sit down for an evening and read through forum posts. In a nutshell (see the earlier post for an example, the wideband-/narrowband configuration thing):

Eval boards are not modules

Sometimes it works but there is a high risk involved (such as, you place your order based on studying board revision X and get revision Y, which is completely different).

If the FPGA is needed only as adapter, have a look at digitizer cards in PCI or PXI form factor.

[zygot]

If you look into the Technical Off-Topic Discussion section you will find a post about all of the third party EVMs that I've had success with. It's by no means a complete compendium and I ( and hopefully others ) will add to that thread when appropriate. The reason for that post is to provide some trail markings for future travellers.

My posts are primarily for the budget constrained crowd.

[zygot]

19 minutes ago, xc6lx45 said:

If the FPGA is needed only as adapter, have a look at digitizer cards in PCI or PXI form factor

Since this was mentioned... a good digital scope can give you 2 or 4 channels of raw ADC data at variable sampling rates. You'll have to be comfortable writing software to parse the output format of very large data files. These are generally in ascii format. Not for every application but if all you want is the data to process it might be useful. I've done it.

 

[Notarobot]

EELE,

Don't waste your time and buy any board before you understanf what is involved in such development. Since you are newbie you have a lot ahead of you. 

In my opinion you need the board with LVDS qualified for data rates required by the ADC chip interface. I recommend to look at the boards from Avnet. They are well documented and I had good experience with a couple of their board. You might learn from Red Pitaya project as well.

Since time is money I would join zygot recommending appropriate digital scope if this is a one time need.

Good Luck!

[xc6lx45]

On 3/16/2019 at 8:25 PM, zygot said:

Since this was mentioned... a good digital scope can give you 2 or 4 channels of raw ADC data at variable sampling rates.

but watch out, the resolution may be closer to 8 bit than the 16 bits mentioned in the original post. This is at least what I got with a GSM signal around 900 MHz (plus a frequency offset I had to correct by resampling, since the average scope does not have a reference clock input). Your mileage may vary.

I had more luck the other way using an RF vector analyzer with IQ inputs as a very expensive oscilloscope but that's about 180 degrees out of phase with the topic ?

[zygot]

16 minutes ago, xc6lx45 said:

but watch out, the resolution may be closer to 8 bit than the 16 bits

Good point. Then again you might be surprised at how few actual usable measurement bits you get out of the "16-bit" or even "8-bit" ADC. Never stop at the sales brochure at the top of every datasheet for converters. Keep on reading, and reading... Even after that read the applications notes to get a sense of why once your ADC is connected to your measurement source you might be losing a lot of those bits. Also understand that the performance of some ADC architectures are very sensitive to clock jitter or noise.

It's not all horrible. Those 'random' LSBs might help your analysis. An old ( even for me... and that's old ) technique is to add white noise into a signal to improve measurements (depends on the application). I use the terms random and white loosely in this context.

Converting analog into sampled digital form and doing analysis of it is a business fraught with danger and not for those of us who tend toward the simple-minded approach to doing things. All of the different converter architectures and implementations have a suite of issues that need to be addressed in order to get close to the sales pitch.

I'm assuming that the person asking the question wants to do everything in the FPGA.

[xc6lx45]

True - the added noise breaks up "coherent" quantization error and spreads it evenly across the bandwidth (where I can usually filter away most of it digitally)

Most analog designers will scratch their heads if given a minimum noise specification for the driver amp but hey, it's physics ?

[EELE]

Hello zygot, xc6lx45, Notarobot

Thank you for your all advice. I haven't seen all of your responses until I logged in forum. I've been checking my email to see if there is any response from Digilent forum, but it looks like Digilent doesn't send any notifications to member via email.

On 3/17/2019 at 9:02 AM, Notarobot said:

In my opinion you need the board with LVDS qualified for data rates required by the ADC chip interface. I recommend to look at the boards from Avnet. They are well documented and I had good experience with a couple of their board. You might learn from Red Pitaya project as well.

 

On 3/16/2019 at 7:51 AM, zygot said:

I've used the Terasic converter boards with Intel based FPGA development boards and they have a good general purpose wide-band analog support.

Thanks Notarobot and zygot. These will be very helpful sources to me. I will definitely look at these.

On 3/16/2019 at 7:51 AM, zygot said:

For Digilent FPGA boards with an FMC connector you have to be careful because there are restrictions using IOSERDES2 and clocking options

Thanks for your info, zygot!

Honestly, I just start learning FPGA, so things seem to be far beyond my knowledge. Yet, I'm not afraid to learn though. In my project, I prefer an evaluation board for ADC rather than designing it because I would save a lot of time (from building circuit, doing calculation, simulation, PCB board, etc. ). Then I use FPGA and Matlab for DSP and displaying the final result. I thought FMC adater from TI would work smoothly with most FPGA (as they state in description) including Xillinx on Digilent. But things seem to be more complicated than I thought.

Do you know if there is any ADC and FPGA boards working best for my project? And what are the maximum resolution and speed of ADC?

Thank you for your time. I really appreciate it.

 

[Notarobot]

Hi EELE

First of all I would recommend PmodAD1 for your experimentation. It contains two ADC chips with 12-bit resolution. I've used it successfully with Zybo 7000 for data acquisition at 1MHz sample rate and it worked at 2 MHz as well.

Then search the forum on Google using request:

site:forum.digilentinc.com/ PmodAD1

You will get a lot of very useful information for making your decisions. I believe this is the shortest path to a knowledge you are looking for. 

[zygot]

12 hours ago, EELE said:

Do you know if there is any ADC and FPGA boards working best for my project?

Well this depends on the requirements of your project, and how you propose to address them. Really high sample rates and extreme data widths appear to address a number of issues, until you look into the details and actual performance that you are likely to obtain using real components. What you need to do for a  start is some analysis about how to deal with the requirements for your particular project. First address the issue of frequency band of interest. Some applications allow for sub-sampling at a lower sampling rate using filters to remove spectral content outside your band of interest. This is common in communications and medical applications. If you need to sample a really wide-band signal, say from DC to 85 MHz then you have your work cut out for you. Converting analog into digital isn't all about the ADC; the analog front end is part of the budget analyses for all of the requirements. As I've mentioned in other posts your analysis of performance includes every component between your signal source and the ADC. A converter's maximum sampling rate is but one, in some cases not even the most significant, criterion for choosing an ADC. For issues of dynamic range a 128-bit ADC would be great! But good luck finding one. Do you realize what kind of signal level the LSB of a 2V pk-pk 16-bit ADC involves? You can deal with fading signal levels using PGAs (programmable gain amp;lifiers), TGC (time-gain control) etc. There are ADC's for ultrasound applications with these built into the device. Again, every component between your signal and the ADC has to be analyzed for it contribution, positive and negative, to your requirement budget analysis. You need to understand that if your 14-bit ADC is set up to sample a signal that varies from 0 to 2V and your signal is 0.5V you don't have a 14-bit ADC any more. There isn't enough space here to deal with all of the important details of analog to digital conversion using actual hardware.

Be aware that those pretty FFT plots that come with every ADC data sheet often involve some pretty bizarre and specific Fs sampling rates and single-tone input signal frequencies in order to show performance of their part in the best possible light,

As I mentioned, Terasic is the only supplier of relatively inexpensive ADC/DAC boards (HSMC connector) that I know of. We're talking 14 bits and 150 MHz ADC 250 MHz DAC sampling rates. They use a fairly generic transformer front end for wide bandwidth. The Cyclone V GT board is nice with PCIe and 2 HSMC connectors. I've described a project that I did using them in the Learn section of this site. You may still have to provide upfront filtering as required. Opal Kelly sells a couple of Syzygy compliant boards and one ADC and one DAC POD. They did their homework as far as providing usable IO for a variety of interface standards; by that I mean they considered clocking, programable IO bank Vcco, and bank pin assignments, and connector with good signal characteristics for their GPIO. Digilent should make a board that is Syzygy compliant. Opal Kelly offers a PMOD Syzygy POD so I'm sure that they would welcome a collaboration.

In terms of converters with advanced IO interfaces such as transceivers or IOSERDES2 you need to verify everything before selecting hardware. Start with understanding your FPGA device resources. Read and understand the reference manuals for IO and clocking. To do IOSERDES2 you need your clock inputs and differential LVDS IO in the same IO bank. High ratio serialization /de-serialization gets messy. If you want to use an ADC evaluation board and an FMC adapter for any particular FPGA board with an FMC connector your have to trace through the signal pin assignments through every connector between your ADC and the FPGA board FMC pin assignments to see if it will work. You might be able to do this with an ADC having a parallel data DDR output ( I have ) but don't expect to be lucky.

I wish I had a really good answer for you but I don't. As I mentioned earlier ADC options for the Xilinx ecosystem, unless you have  a lot of money to burn,  are not great.

BTW, Digilent allows you to send a message directly to any other registered user of their site who will get an email notification.

[EELE]

5 hours ago, zygot said:

BTW, Digilent allow you to send a message to any other registered user of their site and you will get an email notification.

Thank you for your confirmation.

5 hours ago, zygot said:

As I mentioned earlier ADC options for the Xilinx ecosystem, unless you have  a lot of money to burn,  are not great.

In fact, my budget is limited within a few hundred bucks. I think I should do more research about FPGA and hardware before I can ask you any other questions.

Thank you for your all info, zygot! They're really helpful to me.