The Genesys 2 board reference manual on Table 4 lists the max clock rate as ~900MHz and the max data rate as 1800MT/s
1) I looked at the Genesys-2-DMA project to get a handle on how the MIG is configured. Examining the datasheet.txt file in the ip folder for the MIG seems to indicate that the AXI bus width is 256 bits.
Design Clock Frequency : 2500 ps ( 0.00 MHz) <====400MHz
Phy to Controller Clock Ratio : 4:1
Input Clock Period : 5000 ps <====200MHz
Does this mean the AXI interface transfers 256bits, single data rate, with a 200MHz clock?
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SeanS
Hello,
The Genesys 2 board reference manual on Table 4 lists the max clock rate as ~900MHz and the max data rate as 1800MT/s
1) I looked at the Genesys-2-DMA project to get a handle on how the MIG is configured. Examining the datasheet.txt file in the ip folder for the MIG seems to indicate that the AXI bus width is 256 bits.
Design Clock Frequency : 2500 ps ( 0.00 MHz) <====400MHz
Phy to Controller Clock Ratio : 4:1
Input Clock Period : 5000 ps <====200MHz
Does this mean the AXI interface transfers 256bits, single data rate, with a 200MHz clock?
Thanks,
Sean
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