• 0
Sign in to follow this  

Gensys 2 DDR3 Memory Configuration



The Genesys 2 board reference manual on Table 4 lists the max clock rate as ~900MHz and the max data rate as 1800MT/s

1)  I looked at the Genesys-2-DMA project to get a handle on how the MIG is configured.  Examining the datasheet.txt file in the ip folder for the MIG seems to indicate that the AXI bus width is 256 bits.

   Design Clock Frequency         : 2500 ps (  0.00 MHz)       <====400MHz
   Phy to Controller Clock Ratio : 4:1
   Input Clock Period                    : 5000 ps       <====200MHz

Does this mean the AXI interface transfers 256bits, single data rate, with a 200MHz clock?



Share this post

Link to post
Share on other sites

1 answer to this question

Recommended Posts

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this