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Arty A7 UartLite not working . . . is board file wrong?


I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this:



After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the A9 and D10 FPGA pins.

Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD10) and the receive LED (LD9). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.


and looking at this diagram:


Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output.

But here is the  usb_uart interface spec in  the ./board_files/arty-a7-35/E.0/board.xml file :

<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">


<preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>



<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">                            <!--Change to “in”-->


<pin_map port_index="0" component_pin="usb_uart_txd"/>



<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">                              <!--Change to “out”-->


<pin_map port_index="0" component_pin="usb_uart_rxd"/>





So, usb_uart_txd should be "in", usb_uart_rxd should be "out". When I change this, the UartLite serial port works! I tried to change the direction of the pins in the Project HDL "wrapper" to no avail. Please note that this default config is found in the board.xml files for arty, arty-A7 and arty-S7. Do the board.xml files need to be changed? Is there some other way to change pin direction in the Vivado Project?

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Hi @CaptIgmu,

 Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. The input and output signals names are in reference to the PC.

When installing Vivado on a linux OS the cable drivers are not automatically installed. 

1) Here is a xilinx AR showing how install the xilinx/digilent cable drivers. If you have not already. Make sure to be root.

2) Make sure that you have added yourself to the dialout group. Here is a forum thread that shows how to add yourself to the dialout group.

3) Please download Adept 2 here.

                    a) Use Adept 2 from the command line with the command "djtgcfg enum" . What is the terminal text response?

4) Were you root when you installed Vivado?

thank you,


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Hi @jpeyron,

My cable drivers for Linux are installed properly, I've been able to program the Artix-7 FPGA on the Arty A7 board by USB from my PC. That is not the problem. The question is whether the board files need to be corrected for pin direction of TXD and RXD for the Arty boards when adding a usb_uart port to a design. I changed my board.xml file,  it works, I'm just thinking about new Arty users . . .


Thank you,


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Hi @CaptIgmu,

You should not have to alter the board.xml file to swap the pin directions.

The statement "Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC" is accurate but refers to the pins coming out of the FT232. So the FT232's TXD pin is an output to the fpga and carries data received from the PC. Similarly, FT232 pin RXD is an input from the fpga and carries data to be transmitted to the PC.

Following the signal from the FT232 chip into the fpga chip is where it gets interesting.

The definition in the board.xml file you referenced is for an interface. For the ports listed as part of the interface, the sense of direction is from the point of view of the IP block that uses the interface. In this case the AXI_Uartlite IP. 

From the board.xml file, we can see the definitions for the usb_uart interface and also the component that uses the interface. Vivado uses the definitions to generate hdl. 



From the part0_pins.xml file you can see the association with a specific device pin. This gets used to generate constraints.



As a concrete example, assume we have placed an instance of AXI Uartlite into a block design named design_1 (this is from the Pmod MTDS demo).


You can get a sense of how the attributes of the definitions are used by Vivado to generate hdl similar to the following snippets. Vivado either uses an attribute value directly or concatenates it with the names of other modules in the hierarchy to come up with unique names.

For the block design's module file (in my case it is named design_1.v), notice how the values for physical port name "usb_uart_rxd", logical port "RxD", the direction "in" and the component group "UART" are propagated into the hdl.






And for the instance of the AXI Uartlite  (in design_1_axi_uartlite_0_0.vhd) you can see how component ports "rx" and "tx" are associated with "RxD" and "TxD".



The constraint file Vivado built for the AXI_Uartlite component (in MTDS_arty/MTDS_arty.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0_board.xdc) looks like


What this all results in is the FT232 TXD and RXD pins end up getting correctly connected to fpga pins A9 and D10 respectively.

As I type this, I am running the Pmod MTDS demo on my Arty A7-35 and have output from the demo in my terminal window. I did not have to modify any of the board files.


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Hi @kwilber,

Thank you for your explanation. I see the Arty A7 board has been around for a while and I was hard pressed to believe the board.xml file could be wrong this long! Looking through the forums, I see some users having problems getting the UartLite to work and others no problem. I must have a special case because I could not get my design to work until I changed the FPGA direction of TxD and RxD. I will have to try some more projects and try the 16550 uart as an alternative also. Initially I was thinking of  a github pull request to change the board.xml file but realize now I should let this go . . .

Thanks again for your input,


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