I'm planning to implement a video processing design on Nexys Video Board. I need to capture frame_valid, line_valid, data_valid, pixel_clock(40MHz) and 16-bit parallel pixel data from a camera in LVCMOS33 voltage level. I got a few questions about Pmod connectors.
1) In reference manual of Nexys Video Board, it says JA Pmod connector is routed to single ended FPGA pins and it supports <10MHz and LVCMOS33. Is there any problem If I use this port for 40MHz inputs such as pixel_clock, frame_valid or data_valid? (I checked the pin-outs and JA connector pins are not connected to clock capable pins of FPGA.)
2) Reference manual states that JB and JC pins are connected to FPGA differential pair pins and they support >10MHz LVDS25 or TMDS33. Can I use these differential pairs as 2 discrete single ended LVCMOS33 @40MHz inputs? (I'm planning to capture 16-bit parallel video data from these connectors.)
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kami
Hi,
I'm planning to implement a video processing design on Nexys Video Board. I need to capture frame_valid, line_valid, data_valid, pixel_clock(40MHz) and 16-bit parallel pixel data from a camera in LVCMOS33 voltage level. I got a few questions about Pmod connectors.
1) In reference manual of Nexys Video Board, it says JA Pmod connector is routed to single ended FPGA pins and it supports <10MHz and LVCMOS33. Is there any problem If I use this port for 40MHz inputs such as pixel_clock, frame_valid or data_valid? (I checked the pin-outs and JA connector pins are not connected to clock capable pins of FPGA.)
2) Reference manual states that JB and JC pins are connected to FPGA differential pair pins and they support >10MHz LVDS25 or TMDS33. Can I use these differential pairs as 2 discrete single ended LVCMOS33 @40MHz inputs? (I'm planning to capture 16-bit parallel video data from these connectors.)
Best regards,
Kami
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