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Shiro

Multiple driver nets error in Custom IP using Button input on ZYBO

Question

I'm trying to create a hardware using custom ip which capture button status in a register. But, error of multiple driver nets occurred. Could you help me to solve this error please ?
I created project according to ZYBO tutorials as follows:
1. Create project and create new IP.
2. Edit IP: add port and logic in myip_v1_0_S00_AXI.v

------------------

        // Users to add ports here
        input wire [3:0] MY_IN0,
        // User ports ends

------------------------

    // Add user logic here
    always @( posedge S_AXI_ACLK )
    begin
        if ( S_AXI_ARESETN == 1'b0 )
            begin
                slv_reg1 <= 0;
            end 
        else
            begin
                slv_reg1[3:0] <= MY_IN0;
            end 
    end
    // User logic ends

---------------

3. Create Block Design: Add ZYNQ, my IP and external port and connect them.

4. Generate Block Design and Create HDL Wrapper

5. Open erabolated design: Connect myip ports to ZYBO button to generate xdc file.

6. Run synthesis is successfully completed.

7. Run implementation generate several errors.

[DRC MDRV-1] Multiple Driver Nets: Net design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1[0] has multiple drivers: design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1_reg[0]/Q, and design_1_i/myip_0/inst/myip_v1_0_S00_AXI_inst/slv_reg1_reg[0]__0/Q.

I attach the screen shot and my project.

Anyone can help me, please ?


 

 

スクリーンショット 2019-03-12 09.43.44.png

project_6.zip

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3 answers to this question

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Hi Jon,

Thank you for your good advice.  According to the tutorial here, I found that registers "slv_reg[1-4]" should not be written. Instead I prepared other register and change the read process of the register as follows:

Insert these lines: 

    signal my_in0_reg    : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);

and

        -- Users to add ports here
        S_MY_IN0 : in std_logic_vector(3 downto 0);
        -- User ports ends

and

    -- Add user logic here
     process( S_AXI_ACLK ) is
    begin
      if (rising_edge (S_AXI_ACLK)) then
        if ( S_AXI_ARESETN = '0' ) then
          my_in0_reg  <= (others => '0');
        else
          my_in0_reg(3 downto 0) <= S_MY_IN0(3 downto 0);
        end if;
      end if;
    end process;
    -- User logic ends

And, change next line.

--            reg_data_out <= slv_reg1;
            reg_data_out <= my_in0_reg;

Anyway, my probrem is solved. Thank you very much.

Shiro

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Hi @Shiro,

Glad to hear you were able to get your custom IP going. Thank you for sharing what changes you had to make to resolve the multiple driver issue.

cheers,

Jon

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