Spartan7 Code examples

[SivaNageswara Rao]

Dear team,

I am newly started working on spartan 7.

can you please give some sample codes like blank memory access, XADC reading, flash memory, how to use the clock .....

if any documents related to sparton7 VHDL coding please share.

steps to start spartan 7 VHDL coding 

 

 

Regards,

siva 

 

[jpeyron]

Hi @SivaNageswara Rao,

I am not aware of any Spartan 7 specific VHDL documents.  VHDL/Verilog are not board specific.  FPGA4Fun and ASICworld are web sites that will help with using VHDL. 

Here is the resource centers for the Arty S7 and the Cmod S7. Both development boards have the Spartan 7 on them. Each resource center has links to board specific demos/schematics/reference manual and master XDC.  These resources tell you which components you will be able to interact with.  I would also suggest looking through related Xilinx guides and documents like the Spartan 7 family documentation  as well as the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. 

There is Verilog demo projects on each of the resource pages. Unfortunately, I did not find VHDL demos for these boards.

I would look at one of our community members web site hamsterworks done by@hamster. There are many  VHDL projects that you should be able to alter to work with your Arty-S7 like the minimal XADC design.  For the minimal XADC design to work on your Arty-S7 you should only need to alter the XDC file and which AUX channels you will be using.  

thank you,

Jon

[xc6lx45]

Hi,

since you asked for (FPGA) RAM, check out the "inferred memory" concept e.g. here:

https://forums.xilinx.com/t5/Synthesis/UG901-distributed-vs-block-ram-inference/td-p/775730

if you open Vivado main window, then "Tools" menu, there is an option "Language templates". You may also find some useful material there (and some other that is very specialized). One advantage is that these examples are specific for FPGA, whereas generic VHDL instructions may be targeting ASICs or simulation, which are less restricted than FPGA.

[SivaNageswara Rao]

Thank you for your information