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Freshwell

Genesys 2 CONFIG_VOLTAGE and CFGBVS

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Hi all,

I've been developing for the Genesys 2 and am finally starting to get ready to actually load something to the board.

But while creating the bitfile I get the warning from Vivado that I need to set both the config_voltage and the CFGBVS, but I'm not 100% sure what to set these to.

The config_voltage I'm guessing is the IO voltage and thus 3.3v. But for the CFGBVS I have no idea what it should be.

Appreciate any help.

Cheers,

Ernst

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The values required for CFGBVS and CONFIG_VOLTAGE can be found in the schematic for the Genesys2

On Sheet 16 the CONFIG_VOLTAGE for bank 0 is 3.3 volts.

image.png.849f5f26ce587e5bec132bfac779ac2c.png

 

On Sheet 15 you will see the CFGBVS pin is being driven with 3.3 volts (VCCO).

image.png.675e18225414de9f6ef439f1a0359fd0.png

You can find a complete explanation of the settings on page 32 of UG470.

There are several ways these can be set - using tcl, editing the constraint file directly or using the IDE. Please refer to this Xilinx answer record. Ultimately, if specified, they will end up in the constraint file as

image.png.9ed5f09003c6f5154062312bfd1840e0.png

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Hi @Freshwell,

Welcome to the Digilent Forums! 

1) Make sure that you are using the Digilent board files.

2) Make sure you are using the Digilent master XDC. Here is the master XDC for the Genesys 2.  The master XDC individually  constrains each pin including the voltage.

For example:

#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc

this sets the pin E18 to the IO Standard LVCMOS12 which sets the pins voltage to 1.2 V.

In the schematic here on page 12 you will see that E18 is connected to bank 17. Bank 17 is not set to 3.3V. 

3) Please include your HDL and or a screen shot of your Block design, wrapper and xdc file so we can better help with this issue.

4) Please also include a screen shot of the errors you are getting.

thank you,

Jon

PS,

Since many of the pins use a different voltage not 3V3 I do not believe you want to make a blanket constrain like

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Here is the Vivado Design Suite User Guide Using Constraints and Constraints Guide that will explain how to correctly use the XDC in more detail.

 

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Posted (edited)

First of all thank you for your reply!

On 3/8/2019 at 5:06 PM, jpeyron said:

1) Make sure that you are using the Digilent board files. 

2) Make sure you are using the Digilent master XDC. Here is the master XDC for the Genesys 2.  The master XDC individually  constrains each pin including the voltage.

Yes, I'm using both the board files as well as the master XDC.

On 3/8/2019 at 5:06 PM, jpeyron said:

3) Please include your HDL and or a screen shot of your Block design, wrapper and xdc file so we can better help with this issue.

the HDL is going to be a bit much i'm guessing but here is the XDC which is just a slimmed down xdc from the master xdc:

## Clock Signal
set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { clk_in1_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { clk_in1_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
create_clock -add -name clk_in -period 5.00 [get_ports clk_in1_p]
create_clock -add -name RxCK -period 40.00 [get_ports RxCK]

set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clk_in1_p]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks RxCK]

## Ethernet
#set_property -dict { PACKAGE_PIN AK16  IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS15 } [get_ports { MDC }]; #IO_L23P_T3_33 Sch=eth_mdc
set_property -dict { PACKAGE_PIN AG12  IOSTANDARD LVCMOS15 } [get_ports { MDIO }]; #IO_L23N_T3_33 Sch=eth_mdio
set_property -dict { PACKAGE_PIN AH24  IOSTANDARD LVCMOS33 } [get_ports { PhyReset }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
#set_property -dict { PACKAGE_PIN AK15  IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
set_property -dict { PACKAGE_PIN AG10  IOSTANDARD LVCMOS15 } [get_ports { RxCK }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS15 } [get_ports { RxDV }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
set_property -dict { PACKAGE_PIN AJ14  IOSTANDARD LVCMOS15 } [get_ports { Rx0 }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS15 } [get_ports { Rx1 }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
set_property -dict { PACKAGE_PIN AK13  IOSTANDARD LVCMOS15 } [get_ports { Rx2 }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
set_property -dict { PACKAGE_PIN AJ13  IOSTANDARD LVCMOS15 } [get_ports { Rx3 }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS15 } [get_ports { TxCK }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
set_property -dict { PACKAGE_PIN AJ12  IOSTANDARD LVCMOS15 } [get_ports { Tx0 }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
set_property -dict { PACKAGE_PIN AK11  IOSTANDARD LVCMOS15 } [get_ports { Tx1 }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
set_property -dict { PACKAGE_PIN AJ11  IOSTANDARD LVCMOS15 } [get_ports { Tx2 }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
set_property -dict { PACKAGE_PIN AK10  IOSTANDARD LVCMOS15 } [get_ports { Tx3 }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
set_property -dict { PACKAGE_PIN AK14  IOSTANDARD LVCMOS15 } [get_ports { TxEN }]; #IO_L20P_T3_33 Sch=eth_tx_en

 

On 3/8/2019 at 5:06 PM, jpeyron said:

4) Please also include a screen shot of the errors you are getting. 

image.thumb.png.070e4c49165664cfe2566a42ad1cc3b9.png

Edited by Freshwell

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Thanks for your reply @jpeyron.

On 3/12/2019 at 7:00 PM, jpeyron said:

Please try the Genesys 2-OLED demo. Do you get the same results?

I will try it later tomorrow but I'm don't feel it will matter that much since I'm using Vivado 2018.2 instead of 2016.4, which means the environment will already be completely different.

I was thinking of what else could be the problem since this is apparently not a normal issue. As such I've looked deeper into the clocking wizard IP and found out it also has a constraints file, namely the following:

create_clock -period 5.000 [get_ports clk_in1_p]
set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05


set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]

I'll download and install 2016.4 tomorrow and will let you know if the OLED demo works without issue.

Cheers,

Ernst

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Hi @Freshwell,

I looked through our board files, Genesys 2 master xdc and reached out to a co-worked about these warning and the constrains. This warning can be ignored. To fix this warning you can add the below lines to your XDC as @kwilber posted.  Sorry for any confusing my previous post may have caused.

thank you,

Jon

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