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Ahmed Alfadhel

 DIFF_SSTL15 to TMDS_33

Question

Posted (edited)

Hi , 

I am confronting "Conflicting VCC voltages" in Bank 35 ,

so as solution to this error :

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: 
ddr3_sdram_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and sys_clock (LVCMOS33, requiring VCCO=3.300).

I changed the I/O std for ddr3_sdram_ck_p[0] from DIFF_SSTL15 to TMDS_33 .

The question is : What the consequences for this action I made ?

I attached a picture. thank you. 

DIFF_SSTL15 to TMDS_33.JPG

Edited by Ahmed Alfadhel

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Hi @Ahmed Alfadhel,

The DDR3 chip on the Arty A7 (datasheet link for the MT41K128M16) is designed to only operate at either 1.35V or 1.5V and as per the Arty A7 schematic the 1.35V configuration was chosen (you would have to change resistors around to adjust this configuration as mentioned on page 11) and is what our .prj file (github link) for the Arty A7 to configure the DDR3 and MIG IP uses as well.

Going over the voltage input limit for the supply and IO supply voltages are limited to 1.45V (as per Table 41 on page 52 of the datasheet I linked) and if those maximum limits are exceeded, the input levels will be governed by DDR3 specifications (as per Note 5 on page 52), which limit the maximum supply voltages to 1.575V (with respect to Vss, as per Table 7 on page 26). Either way, using a clock signal that would be fed into the DDR3 chip that will go up to 3.3V will wildly overshoot the acceptable input levels (limitations detailed on page 57 in Table 46 of the datasheet, generally limited to 0.4V for a very small amount of time), effectively frying that pin on the DDR3 chip and possibly more.

I would recommend carefully following voltage limitations of both the DDR3 chip and the Artix 7 if you are going to choose to configure and constrain the FPGA pins yourself.

Thanks,
JColvin

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@Ahmed Alfadhel,

The real answer is that if you have both sys_clk and ddr3_sdram_ck* on the same bank, your pinout is still wrong.  sys_clk is on a 3.3V bank, ddr3_sdram_ck* is on a 1.35V bank.  If you give Vivado the wrong pins for these three wires, it will complain about the wrong voltage standard.  Go back and set these pins to their right values.

If you want a quick way to do this, consider using this UCF file to load the pin definitions directly into the MIG DDR3 SDRAM controller generator.

Dan

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