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hello.parth

UDP IP Ethernet on Nexys Video from PC to FPGA

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Hello All,

I am currently working on Nexys Video Ethernet.

I want to transmit and recieve UDP  packets between PC and  Nexys Video FPGA . Is it possible to perform without Microblaze? 

How to send UDP Packets from PC to FPGA.? 

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Hi @hello.parth,

The Ethernet IP cores use the AXI BUS. You would need to implement the AXI BUS communication to interact with the Ethernet IP Cores.  This is not an easy task.  

You do not need to use Microblaze or the Ethernet IP Cores to use the ethernet on the Nexys Video.  Here is a community members( @hamster) VHDL GigabitTX project using the Nexys Video. 

 

thank you,

Jon

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Hello, Jpeyron

Yes, I have implemented Gigabit Tx by @Hamster in Both VHDL and Verilog. This is only for transmission from FPGA to PC

Can you Help us for Receive part from PC to FPGA?

How to begin communication from PC to FPGA. I want to send some commands using UDP from PC to FPGA.

It will be great help

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On 3/6/2019 at 4:30 AM, hello.parth said:

I want to transmit and recieve UDP  packets between PC and  Nexys Video FPGA . Is it possible to perform without Microblaze?

I've been bothered by this question since it was posted.

Is it possible to implement logic in hardware using and HDL to implement the basic requirements to send and receive UDP packets for a direct connection between your FPGA board and a computer? Sure. You can find a few implementations that will show you what the necessary functionality is. If the path between your computer and your FPGA board is not direct and your packets are not in order or get fragmented then things get complicated, but still doable. The question then becomes is it worth doing without a soft-processor? Only you can answer that question.

I would suggest that you should have a practical understanding of all of the Ethernet layers. You can study the code for light-weight Ethernet stacks available for hard or soft processors to see what you need to support. Sending UDP ( or any packet structure you can imagine ) between two FPGA boards is relatively easy and can be done with minimal effort. Once you start dealing with a full-blown OS stack things can get quite complicated. I doubt that you care about this for your project but it is possible to avoid the PC Ethernet port on your computer and still implement communication between your PC and an FPGA target(s) using the target Ethernet PHY(s).

Opencores has some interesting projects [some involving MACs and some not]. The Digilent Project Vault has a couple of projects that might help. There will be those who disagree but I suggest becoming knowledgeable with how Ethernet connectivity works is a precondition for trying to implement it in an embedded application using logic or software tools.

[edit] You might find that using the parallel USB 2.0 interface on the Nexys Video is easier and possibly a better way to connect your board to a PC; unless, of course, you have a requirement for UDP packets.

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FIrst of All Yes, We have requirement of UDP Packets for both Transmit and Receive. Something like I want to send command from PC to FPGA after that it will start sending UDP packets. (For Example: I will send command to start video from PC to FPGA then I will send UDP Packets of Pixels data from FPGA)

One more thing is i am looking for is only single point communication between PC to FPGA. No network switches in between  (No multi-FPGA or any cluster )

@zygot : It will be great help if you have any example for FPGA Implementation with soft-processor like micro-blaze. Currently I am using Nexys-Video which supports Microblaze.

We have implemented Gigabit Tx by @Hamster in verilog and we are able to transmit data and we can visualize all packets on wire sharks.  Now, we would like to learn how to communicate from PC to FPGA but not able to find proper examples.

 

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Posted (edited)

@hello.parth

You don't need a soft processor to send and receive data from a PC to your FPGA Ethernet PHY. There are examples in Opencores. If you look around in in Digilent's Project Vault Vonmuller has a UDP echo server ( 10/100 ). It needs some work in the PHY programming interface but with Digilent boards you don't need to write PHY registers. I have a more recent Gigabit Ethernet PHY Tester project nearby with a VHDL  example for the Nexys Video board DUT. At least you can see how to use the PHY for send and receive. These projects have been available for quite some time and neither has generated significant feedback even though a number of people ask how to get connectivity between their PC and and FPGA board using Ethernet.  By studying such projects you can figure out what you need to do.

There are some details that have to be taken care of, like properly resetting the PHY. Fortunately, Digilent is nice enough to bring the PHY into a usable state for Gigabit operation out of reset. Once the data paths between the PHY and the FPGA logic are working it's just a matter of parsing and forming UDP packets. Since one end of the Ethernet link is a PC you will have to implement CRC, ARP advertising, and ARP response packets; unless you want to write a driver to override the PC OS Ethernet stack driver... you don't. Supporting only Gigabit Ethernet is a big simplification. You should be able to understand why your PC has to maintain order in its Ethernet communications.

I really don't have any interest in writing an Ethernet stack in HDL ( there are some who have in OpenCores ) so I don't have  'plug and play' code to give you. You can figure this out on your own, with the few hints in the cited references. Debugging the Ethernet traffic in your FPGA will be a useful challenge. Once you get a few details right the rest is straightforward.

I don't understand why people don't take the time to work through the Project Vault resources. I do know that the one-sided interaction there makes the whole experience less useful everyone.

 

Edited by zygot

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True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...

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