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Ahmed Alfadhel

Conflicting Voltages in Bank Arty-A7

Question

On 9/10/2015 at 1:14 AM, Commanderfranz said:

Hi Tony,

What that error means is that you cannot have two different I/O standards, input output voltage standards in the same bank. To fix it you need to go to your XDC file for the project and change the I/O standards that say LVCMOS18 to LVCMOS33.

You can always use the I/O standards listed in the Basys 3 master XDC file on the product page.

Kaitlyn

Hi @Commanderfranz,

How to solve this error:

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: 
ddr3_sdram_0_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and sys_clock (LVCMOS33, requiring VCCO=3.300)

Any comments I will appreciate it.

thanks

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Posted (edited)

The answer to your question is in two documents: the schematic for your FPGA board and the IO User's Guide. For Series 7 devices this is UG471. Anyone wanting to make their own interfaces must understand the rules [ there are a lot of rules so read the whole manual]. All IO pins are connected to an IO bank. Every IO Bank can be powered with a different Vcco to suit the IOSTANDARD being used. There are rules for mixing IOSTANDARD assignments for any bank. Be aware that some boards, like the Genesys2, have HR and HP banks which further complicate the rules for using IO.

As I've pointed out before, many times in fact, the differential "high speed" PMODs are almost useless since all of them are connected to IO Banks powered by Vcco = 3.3V. There are no 3.3V differential IOSTANDARDs supported by Series 7 devices. Spartan 6 and Spartan 3 do support LVDS_33 or LVDS_25 depending on what the Vcco is . For Digilent boards with FMC connectors they use Vadj which allows the user to select from an a wider range of IOSTANDARD to use LVDS directly. None of the Digilent boards with PMODs, that I know of, use Vadj or user selectable Vcco for PMOD IO banks. For LVDS a further complication is that a parallel termination is required and that termination should be as close to the receiving end as possible. HR LVDS supports internal termination.

Does this mean that your are completely stuck if your board doesn't directly support the logic that you want to use? No necessarily, but you will have to spend some money getting it right. Xilinx has application notes to help with that.

Last thought on the subject. Just getting the IO Vcco and logic right may not be enough to implement an interface. There are rules for clocking that may impact your design. There's a user Guide for clocking.

For anyone interested in doing differential interfaces and not able to make their own FMC mezzanine board, Opal Kelly has 2 boards that support the Syzygy specification. They've clearly read the documents and did their homework and have implemented a truly usable POD interface.

 

Edited by zygot

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@zygot,

@Ahmed Alfadhel is not using a Basys3 board, and so this is really a bad example of attaching one question to another post.  @Ahmed Alfadhel appears to be using an Artix-A7 board.  In that case, the sys_clk is properly constrained, but he may well have some of the DDR3 I/O pins improperly constrained.  These are the pins located on Bank 35.

I think the problem in this case is that @Ahmed Alfadhel has improperly constrained in DDR DQS pins.  For example, ddr3_dqs_[0] should be set to pin N2, not to A6.

Compounding the problem is the way these pins are hidden in a "board definition file" rather than in the XDC file, making it likely to have conflicting pin definitions.

@Ahmed Alfadhel,

If you are following Digilent's instructions, you might want to double check that you have the appropriate board definition file.  If you are trying this on your own, using only an XDC file, then you might find these instructions valuable.  Also, I would recommend you not attach unrelated issues to old posts.  Perhaps the Digilent staff might be kind enough to separate these two issues into separate forum posts--since they really are quite different.  For example, the Basys3 board doesn't have the DDR3 memory which is the source of your pin-connection troubles.

Dan

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@D@n

Well I'm really confused because the original post and first couple of answers appear to be missing to this thread..

However, I'll enter a mea cupa to providing a general answer to the original post that doesn't not directly address it. The fact that it was asked implies that a general reply might be warranted.... and might be helpful to anyone new to FPGA development as are so many visitors to this site.

cheers!

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Hi @D@n,

I am sorry for the inconvenient.

By the way, 

27 minutes ago, D@n said:

For example, ddr3_dqs_[0] should be set to pin N2, not to A6

 How did you determine that ?

Thanks.

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@Ahmed Alfadhel,

That "machine readable" board XML file for the Arty is actually pseudo-human readable.    Feel free to download it.  The current link for those files appears to be here.  You might find it with a ".prj" extension.

@zygot,

It looks like the Digilent staff took my advice/suggestion and moved this into its own thread.  (Thank you!)  That would be why you aren't seeing the (irrelevant) history any more.

Dan

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Hi @zygot,

23 hours ago, zygot said:

There are rules for clocking that may impact your design. There's a user Guide for clocking.

Kindly, I want the User Guide name for clocking.

Thanks in advance.

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@Ahmed Alfadhel

If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly.

Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.

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