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No thing is appearing at Tera Term !


Go to solution Solved by Ahmed Alfadhel,

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Hi @jpeyron

I am using Tera Term for debuging my program. However, this time is no thing is appearing at Tera Term window !

Does it is possible; the reason for this issue since I fed the microblzae with 333 MHz clock signal ? If so , what should I do ?

I attached a snapshot for my block design.

this is my program that I wrote in Xilinx Eclipse SDK :

/*
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/

/*
*
*
* This file is a generated sample test application.
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* SDK application project when you run the "Generate Libraries" menu item.
*
*/

#include <stdio.h>
#include <string.h>
#include "xparameters.h"
#include "xil_cache.h"
#include "xiomodule.h"
#include "iomodule_header.h"
#include "xil_printf.h"

#include "PmodDA3.h"

//Global parameters
PmodDA3 myDevice;
u32 data;
u32 Hops_reading;

int main ()
{
int delay_count;

Xil_ICacheEnable();
Xil_DCacheEnable();

//part 1 testing peripherals
print("---Entering main---\n\r");

{
XStatus status;

print("\r\nRunning IOModuleSelfTestExample() for iomodule_0...\r\n");

status = IOModuleSelfTestExample(XPAR_IOMODULE_0_DEVICE_ID);

if (status == 0) {
print("IOModuleSelfTestExample PASSED\r\n");
}
else {
print("IOModuleSelfTestExample FAILED\r\n");
}

print("\r\nRunning IOModuleSelfTestExample() for PmodDA3_0...\r\n");
status = IOModuleSelfTestExample(XPAR_PMODDA3_0_DEVICE_ID);
if (status == 0) {
print("IOModuleSelfTestExample 2 PASSED\r\n");
}
else {
print("IOModuleSelfTestExample 2 FAILED\r\n");
}
}


print("---Exiting Testing---\n\r");

 


// Part 2 Generating The Frequency Hops

XIOModule gpi;

DemoInitialize(); // 1st step DAC

// initialize our GPIO's
data = XIOModule_Initialize(&gpi, XPAR_IOMODULE_0_DEVICE_ID);
data = XIOModule_Start(&gpi);

while(delay_count < 500000000)
{
Hops_reading = XIOModule_DiscreteRead(&gpi, 1); // Perform Hop Reading


//delay_count = 0;

//DemoRun(); // 2nd step DAC


DA3_WriteSpi(&myDevice, 0x3A, &Hops_reading, sizeof(Hops_reading));

// while (delay_count < 50000000)
delay_count++;
}

 

print("---End of this program---\n\r");
DemoCleanup(); // 3rd step DAC


Xil_DCacheDisable();
Xil_ICacheDisable();

return 0;
}

void DemoInitialize()
{
EnableCaches();
DA3_begin(&myDevice, XPAR_PMODDA3_0_AXI_LITE_SPI_BASEADDR);
}

void DemoCleanup() {
DA3_end(&myDevice);
DisableCaches();
}

 


void EnableCaches() {
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheEnable();
#endif
#endif
}

void DisableCaches() {
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheDisable();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheDisable();
#endif
#endif
}

________________________________________________________________

I am looking forward your help.

Thanks in advance.

System_Design_BFSK.png

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7 answers to this question

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Hi @Ahmed Alfadhel,

To confirm you were getting uart communication. Then you alter the frequency to 333 MHZ the uart stopped. I would think that changing the frequency could be the issue. I would suggest altering back to the original frequency and then testing the uart. 

The digilent board files are made to correctly configure the ddr and microblaze among other thing. 

Why are you changing the frequency? 

thank you,

Jon

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Hi @Ahmed Alfadhel,

I followed the FPGAdeveloper video as best as i could using Digilent's board files. When selecting Application in block automation of the microblaze it grays out one of the cache choices. The microblaze clk shows 100 MHz after finishing block automation. I generated a  Vivado 2018.2 Arty A7 35T microblaze uart project here using the Arty - Getting Started with Microblaze as reference. The clk is 100 MHz. I have attached screen shots showing this below.

thank you,

Jon

Arty_A7_333_mhz_4.jpg

Arty_A7_333_mhz_3.jpg

Arty_A7_333_mhz_2.jpg

Arty_A7_333_mhz_1.jpg

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Hi @Ahmed Alfadhel,

I re-opened the project i linked and you are correct the clk off of the microblaze is at 83 mhz. Sorry for the mistake. It is not 100 MHz but rather 83 MHZ.   The clock connection is the same setting in the FPGAdevelopers's video as well. This is the suggested setting for configuring the Arty-A7-35T.  Its my understanding that we chose the 166.667 MHz  clock in the clocking wizard do to an issue with the DDR. 

To try and possibly gain additional performance by increasing this clock you will  need to research configuring the microblaze . You will also need to research all of the other components using this clock and configure them appropriately.    

thank you,

Jon

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