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Hi all

I'm currently working on a project based on ultrasound. I've created a pulsetransmitting board already which hooks into the zedboards FMC-LPC connector (I needed 64 high-speed channels), yet now I need to make a receiving side as well. Since returning signals are in the range of 250-300kHz, I was looking into ADCs of around 1MSps@12 or 14bits. (max. 4 channels needed)

Now is the problem that I can't find any spec on the frequency the zedboard PMODs can handle. Is it possible to have speeds of approx 20MHz or is this out of range of the (high-speed) PMOD connectors? 
Would it be a better idea to make a board with a female-male connector on top of each other so I can pass the signals which need to be passed to the previous made board (as I only need a couple of its transmitting channels, stack the boards with the FMC-LPC connector) and use the other connections for an ADC board, since the FMC should be capable of higher speeds?

any thoughts?

Thanks!

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Hi @devriese.wouter,

Here is the Zedboard's reference manual which goes into detail that two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs.  The on board XADC does 2 channels, 12 bits at 1 MSPS  which is described the  7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. Also the Pmod AD1 is a 2 channel, 12 bit, 1 MSPS ADC as well. 

I would suggest using the Zedboard's on-board XADC first and make sure this will work for you. If so them I would then look into using the Pmod AD1 as well. You can use the Pmod AD1 on any of the PL Pmod Ports.

thank you,

Jon

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@devriese.wouter

You might want to look at the LTC2311 and LTC2323 families of ADC. They have a good 3dB bandwidth, 12 to 16 bit versions, 5 Msps, and an SPI interface that supports single-ended or differential signalling. You can make your own board that fits 2 of these onto each of the differential PMODs to get 4 channels. I haven't used the devices but what I've read looks promising.

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@devriese.wouter

The following, extracted from another post that I recently made,  might be better attached to my previous advice about selecting an ADC for use with PMODs:

"As I've pointed out before, many times in fact, the differential "high speed" PMODs are almost useless since all of them are connected to IO Banks powered by Vcco = 3.3V. There are no 3.3V differential IOSTANDARDs supported by Series 7 devices. Spartan 6 and Spartan 3 do support LVDS_33 or LVDS_25 depending on what the Vcco is . For Digilent boards with FMC connectors they use Vadj which allows the user to select from an a wider range of IOSTANDARD to use LVDS directly. None of the Digilent boards with PMODs, that I know of, use Vadj or user selectable Vcco for PMOD IO banks. For LVDS a further complication is that a parallel termination is required and that termination should be as close to the receiving end as possible. HR LVDS supports internal termination.

Does this mean that your are completely stuck if your board doesn't directly support the logic that you want to use? No necessarily, but you will have to spend some money getting it right. Xilinx has application notes to help with that.

Last thought on the subject. Just getting the IO Vcco and logic right may not be enough to implement an interface. There are rules for clocking that may impact your design. There's a user Guide for clocking.

For anyone interested in doing differential interfaces and not able to make their own FMC mezzanine board, Opal Kelly has 2 boards that support the Syzygy specification. They've clearly read the documents and did their homework and have implemented a truly usable POD interface."

You can still use the differential PMODs with the ADCs listed above but not using the differential interface. Note that to achieve a 5 Msps rate you need to use an SCK of 105 Mhz... which is likely too high for the normal "slow" PMODs. As with any ADC you need to read the entire datasheet and any other relevant material closely before trying to implement a design.

Digilent mentions in some of their FPGA board reference manuals that the differential PMOD traces are routed differentially, which is good for reducing common-mode noise, but not so good when used as single-ended lines. Assigning all _n pins to ground helps with single-ended interfaces for these PMODs but you only get 4 interface signals to work with.

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