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Basys 3 - xadc_wiz_0


danielts

Question

Hello people! I'm trying to configure an ADC on a basys 3 board using xadc_wiz_0. I have been reading this datasheet: https://cdn.instructables.com/ORIG/FDN/O5OZ/IWMMH03D/FDNO5OZIWMMH03D.pdf#G5.287914 and on page 34 I am getting a little optimistic. Can I configure the basys 3 to do analog to digital converting on my pmod encoder from the span: 0V to 3.3V by using the power supply as reference? If so how? I'm a beginner to FPGA, every bit of help is appreciated!

- The port map I'm trying to do if that helps anything:

	signal AdressBus        :   STD_LOGIC_VECTOR (6 downto 0) := "0011110";
    signal EnableInt        :   STD_LOGIC := '1';
    signal InputDataBus     :   STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
    signal writeEnable      :   STD_LOGIC := '0';
    signal outPutBusDataMSB :   STD_LOGIC_VECTOR (7 downto 0);
    signal outPutBusDataLSB :   STD_LOGIC_VECTOR (7 downto 0);
    signal resetSignal      :   STD_LOGIC := '0';
    signal drdy             :   STD_LOGIC := '0';      
    
    -----------------------------------------------------------------
    
    ADCimpl: xadc_wiz_0
    port map(
            daddr_in                    => AdressBus,                           -- se datablad side 45
            den_in                      => EnableInt,                           -- Enable device
            di_in                       => InputDataBus,                        --
            dwe_in                      => writeEnable,                         -- Unused, so 0
            do_out (15 downto 8)        => outPutBusDataMSB(7 downto 0),        -- Output DataBus MSB
            do_out (7 downto 0)         => outPutBusDataLSB(7 downto 0),        --
            drdy_out                    => drdy,                                -- Data ready signal for the dynamic reconfiguration port
            dclk_in                     => clk,                                 -- Clock input for the dynamic reconfiguration port
            reset_in                    => resetSignal,                         -- Reset signal for the System Monitor control logic
            vauxp14                     => ADC(0),                              -- Forskellen mellem disse to.
            vauxn14                     => ADC(1),                              --
            busy_out                    => open,                                --
            channel_out                 => open,                                --
            eoc_out                     => EnableInt,                           -- End of conversion signal
            eos_out                     => open,                                --
            alarm_out                   => open,                                --
            vp_in                       => '0',                                 --
            vn_in                       => '0'                                  --
            );

 

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Hi @danielts,

Welcome to the Digilent Forums!

1) The XADC has a 1V P-P input swing. The XADC measures between 0V and 1V in unipolar mode, or -0.5 to +0.5 in bipolar mode. With that in mind, you would not be able to measure 0 to 3V. 

 2) If you have not i would suggest to look through the XADC Wizard v3.0 LogiCORE IP Product Guide and 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide.

3) Here is a VHDL Basys 3 XADC project done by a community member( @hamster) .

4) Here is the Digilent Verilog Basys 3 XADC project as well. 

thank you,

Jon

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