PS SPI failing self test on Cora 10

[RallyTronics]

I am trying to get PS SPI up and going on my Cora 10 board using 2018.2.  The pins are routed through EMIO.  I have tied the SPI0_SS_I signal high as per AR58294 .  It fails the following portion of the test: 

 

    Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
                 XSPIPS_SR_OFFSET);
    if (Register != XSPIPS_ISR_RESET_STATE) {
        return (s32)XST_REGISTER_ERROR;
    }

 

I would appreciate any help on getting to the bottom of this. 

 

My pin constraints:

## Pmod Header JA
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { SPI0_SS_O_0 }]; #IO_L17P_T2_34 Sch=ja_p[1]
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { SPI0_MOSI_O_0 }]; #IO_L17N_T2_34 Sch=ja_n[1]
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { SPI0_MISO_I_0 }]; #IO_L7P_T1_34 Sch=ja_p[2]
set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { SPI0_SCLK_O_0 }]; #IO_L7N_T1_34 Sch=ja_n[2]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SPI0_SS1_O_0 }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { SPI0_SS2_O_0 }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { CAN_0_0_rx }]; #IO_L22P_T3_34 Sch=ja_p[4]
set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { CAN_0_0_tx }]; #IO_L22N_T3_34 Sch=ja_n[4]

## Pmod Header JB
set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { SPI1_SS_O_0 }]; #IO_L8P_T1_34 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { SPI1_MOSI_O_0 }]; #IO_L8N_T1_34 Sch=jb_n[1]
set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { SPI1_MISO_I_0 }]; #IO_L1P_T0_34 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { SPI1_SCLK_O_0 }]; #IO_L1N_T0_34 Sch=jb_n[2]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { SPI1_SS1_O_0 }]; #IO_L18P_T2_34 Sch=jb_p[3]
set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { SPI1_SS2_O_0 }]; #IO_L18N_T2_34 Sch=jb_n[3]
set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { CAN_1_0_rx }]; #IO_L4P_T0_34 Sch=jb_p[4]
set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { CAN_1_0_tx }]; #IO_L4N_T0_34 Sch=jb_n[4]
 

 

[jpeyron]

Hi @RallyTronics,

I had an engineer from content and an engineer from testing look at this post. They do not see anything specifically wrong or out of place nor do I. They both suggested the you would be better off reaching out to Xilinx support about this issue.

thank you,

Jon

[bkzshabbaz]

Did you ever get a resolution to this either by yourself or from Xilinx support?  I'm running into the same issue as you.

[bkzshabbaz]

I think I've figured out the problem.  I had to enable interrupts in the PS.  The interrupts are enabled in PS-PL Configuration -> General -> Interrupts -> PS to PL -> SPI