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Zybo-Z7-20-base-linux - Vivado 2017.4 issues


Hi Guys,

The Zybo-Z7-20-base-linux project seems broken, or I am going something wrong:

git clone --recursive https://github.com/Digilent/Zybo-Z7-20-base-linux.git

In Vivado 2017.4 tcl command window:

source ./create_project.tcl


Log from this:

cd /home/andrewcapon/Development/Zybo/Zybo-Z7-20-base-linux/proj
source ./create_project.tcl
# set proj_name "base-lin"
# if {[info exists ::create_path]} {
# 	set dest_dir $::create_path
# } else {
# 	set dest_dir [file normalize [file dirname [info script]]]
# }
# puts "INFO: Creating new project in $dest_dir"
INFO: Creating new project in /home/andrewcapon/Development/Zybo/Zybo-Z7-20-base-linux/proj
# cd $dest_dir
# set part "xc7z020clg400-1"
# set brd_part "digilentinc.com:zybo-z7-20:part0:1.0"
# set origin_dir ".."
# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
# set src_dir $origin_dir/src
# set repo_dir $origin_dir/repo
# create_project $proj_name $dest_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/andrewcapon/Xilinx2017.4/Vivado/2017.4/data/ip'.
create_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6164.723 ; gain = 89.504 ; free physical = 152 ; free virtual = 13506
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $proj_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "part" $part $obj
# set_property "board_part" $brd_part $obj
# set_property "simulator_language" "Mixed" $obj
# set_property "target_language" "VHDL" $obj
# set_property "corecontainer.enable" "0" $obj
# set_property "ip_cache_permissions" "read write" $obj
# set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/andrewcapon/Development/Zybo/Zybo-Z7-20-base-linux/repo'.
# add_files -quiet $src_dir/hdl
# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
# add_files -fileset constrs_1 -quiet $src_dir/constraints
# if {[string equal [get_runs -quiet synth_1] ""]} {
#   create_run -name synth_1 -part $part -flow {Vivado Synthesis 2017} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#   set_property flow "Vivado Synthesis 2017" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "part" $part $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#   create_run -name impl_1 -part $part -flow {Vivado Implementation 2017} -strategy "Performance_ExtraTimingOpt" -constrset constrs_1 -parent_run synth_1
# } else {
#   set_property strategy "Performance_ExtraTimingOpt" [get_runs impl_1]
#   set_property flow "Vivado Implementation 2017" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "part" $part $obj
# set_property -name "steps.route_design.args.directive" -value "RuntimeOptimized" -objects $obj
# current_run -implementation [get_runs impl_1]
# puts "INFO: Project created:$proj_name"
INFO: Project created:base-lin
# set bd_list [glob -nocomplain $src_dir/bd/*/*.bd]
# if {[llength $bd_list] != 0} {
#   add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
#   open_bd_design [glob -nocomplain $src_dir/bd/*/*.bd]
#   set design_name [get_bd_designs]
#   set file "$origin_dir/src/bd/$design_name/$design_name.bd"
#   set file [file normalize $file]
#   set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
#   if { ![get_property "is_locked" $file_obj] } {
#     set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
#   }
#   # Generate the wrapper 
#   set design_name [get_bd_designs]
#   add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]
#   set obj [get_filesets sources_1]
#   set_property "top" "${design_name}_wrapper" $obj
# }
Adding cell -- digilentinc.com:IP:PWM:2.0 - pwm_rgb
Adding cell -- digilentinc.com:ip:axi_dynclk:1.0 - axi_dynclk_0
Adding cell -- analog.com:user:axi_i2s_adi:1.0 - axi_i2s_adi_0
Adding cell -- digilentinc.com:ip:dvi2rgb:1.8 - dvi2rgb_1
Adding cell -- digilentinc.com:ip:rgb2dvi:1.4 - rgb2dvi_1
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_led
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_sw_btn
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_video
Adding cell -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma_0
Adding cell -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma_1
Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_in
Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_out
Adding cell -- xilinx.com:ip:clk_wiz:5.4 - clk_wiz_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_100M
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_133M
Adding cell -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_fclk1
Adding cell -- xilinx.com:ip:v_axi4s_vid_out:4.0 - v_axi4s_vid_out_0
Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_in
Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_out
Adding cell -- xilinx.com:ip:v_vid_in_axi4s:4.0 - v_vid_in_axi4s_0
Adding cell -- xilinx.com:ip:xadc_wiz:3.3 - xadc_wiz_0
Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_1
Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_0
Adding cell -- xilinx.com:ip:axi_iic:2.0 - axi_iic_0
Adding cell -- xilinx.com:ip:xlslice:1.0 - PS_GPIO_0
Adding cell -- xilinx.com:ip:xlslice:1.0 - PS_GPIO_2
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_eth
Adding cell -- xilinx.com:ip:xlslice:1.0 - PS_GPIO_3
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - axi_data_fifo_0
Adding cell -- xilinx.com:ip:mipi_csi2_rx_subsystem:3.0 - mipi_csi2_rx_subsystem_0
Adding cell -- xilinx.com:ip:v_frmbuf_wr:2.0 - v_frmbuf_wr_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_1/aRst_n(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /axi_i2s_adi_0/DATA_CLK_I(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /dvi2rgb_1/aPixelClkLckd(undef) and /proc_sys_reset_0/aux_reset_in(rst)
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s01_regslice
Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice
Successfully read diagram <system> from BD file <../src/bd/system/system.bd>
open_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 6342.469 ; gain = 70.484 ; free physical = 167 ; free virtual = 13357
WARNING: [Vivado 12-818] No files matched '*/home/andrewcapon/Development/Zybo/Zybo-Z7-20-base-linux/src/bd/bd_0ac3 system/bd_0ac3 system.bd'
ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
update_compile_order -fileset sources_1


Generating bitstream:

launch_runs impl_1 -to_step write_bitstream -jobs 12

[filemgmt 20-730] Could not find a top module in the fileset sources_1.
Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow.

[Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top <name> [current_fileset]).



Has anyone got any ideas, I'm guessing the problem is:

WARNING: [Vivado 12-818] No files matched '*/home/andrewcapon/Development/Zybo/Zybo-Z7-20-base-linux/src/bd/bd_0ac3 system/bd_0ac3 system.bd'


Thanks for any help.



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2 answers to this question

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From the error message you posted, it looks like the create_project.tcl script errored out and did not create the wrapper for the block design.

In the sources window, expand the "Design sources" branch. You should see a "system" node. Right click on that and the context menu should have "Create HDL wrapper...". Click on that and vivado will create a top level module to wrap the block design.

Once you have the wrapper, you should be able to click on "Generate bitstream" in the flow navigator.

In the snip that follows, I reproduced your error. You can see the tail end of the create_project.tcl including the error you observed. You can also see the additional output when I used "Create HDL wrapper..." and the "Generate bitstream". The bitstream was created successfully.


Edited by kwilber

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Thanks very much for the info, as you say Generate bitstream works when the HDL wrapper is created.


Many thanks




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