I have been working on a benchmark code of AES128 for few days. When I import the project in vivado, synthesis and implementation run fine, but when i generate bitstream, i get error in implementation. I am using zedboard xc7z020clg484-1
I get the following error in my log.
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75883 ; free virtual = 95116
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75886 ; free virtual = 95119
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1820.000 ; gain = 352.055 ; free physical = 75897 ; free virtual = 95130
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1894.148 ; gain = 0.000 ; free physical = 75796 ; free virtual = 95029
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
70 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:40 . Memory (MB): peak = 1894.148 ; gain = 426.207 ; free physical = 75847 ; free virtual = 95080
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.148 ; gain = 0.000 ; free physical = 75847 ; free virtual = 95080
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/s2256800/AES128/AES128.runs/synth_1/aes_ip.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file aes_ip_utilization_synth.rpt -pb aes_ip_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 11:50:46 2019...
Please help me where i got wrong. Thanks in advance.
Question
Hunaina
Hello,
I have been working on a benchmark code of AES128 for few days. When I import the project in vivado, synthesis and implementation run fine, but when i generate bitstream, i get error in implementation. I am using zedboard xc7z020clg484-1
I get the following error in my log.
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75883 ; free virtual = 95116
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75886 ; free virtual = 95119
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1820.000 ; gain = 352.055 ; free physical = 75897 ; free virtual = 95130
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1894.148 ; gain = 0.000 ; free physical = 75796 ; free virtual = 95029
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
70 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:40 . Memory (MB): peak = 1894.148 ; gain = 426.207 ; free physical = 75847 ; free virtual = 95080
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.148 ; gain = 0.000 ; free physical = 75847 ; free virtual = 95080
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/s2256800/AES128/AES128.runs/synth_1/aes_ip.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file aes_ip_utilization_synth.rpt -pb aes_ip_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 11:50:46 2019...
Please help me where i got wrong. Thanks in advance.
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