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stfarley

ZyboZ7 Ethernet config

Question

Hi,

I am using the ZyboZ7 to test a prototype a design in Vivado 2018.3. I have everything working but ethernet. What I can't quite figure out is the connections for CLK125, Rest and Interrupt.

The ref guide shows Reset as a zynq output and CLK125 as an input in Fig 5.1, but both as bidirectional Figure 10.1. If I load up the DMA example design the pins identified for these have no connections.

If I bring up my design in SDK and generate the Peripheral test it stalls on the ethernet interrupt test. 

I am just wondering how these signals are supposed to be connected.

 

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Hi @jpeyron

Here is the console output.

---Entering main---

 

Running ScuGicSelfTestExample() for ps7_scugic_0...

ScuGicSelfTestExample PASSED

ScuGic Interrupt Setup PASSED

Press button to Generate Interrupt

No button pressed.

 

Running IicSelfTestExample() for axi_iic_0...

IicSelfTestExample PASSED

 

Running DcfgSelfTestExample() for ps7_dev_cfg_0...

DcfgSelfTestExample PASSED

 

Running XDmaPs_Example_W_Intr() for ps7_dma_s...

Test round 0

XDmaPs_Example_W_Intr PASSED

 

Running Interrupt Test  for ps7_ethernet_0...

Error setup phy loopback

Length mismatch

EmacPsDmaIntrExample FAILED

 

Running QspiSelfTestExample() for ps7_qspi_0...

QspiPsSelfTestExample PASSED

 

Running AxiDMASelfTestExample() for axi_dma_0...

AxiDMASelfTestExample PASSED

 

Running ScuTimerPolledExample() for ps7_scutimer_0...

ScuTimerPolledExample PASSED

 

Running Interrupt Test  for ps7_scutimer_0...

ScuTimerIntrExample PASSED

 

Running Interrupt Test  for ps7_scuwdt_0...

ScuWdtIntrExample PASSED

---Exiting main---

 

Thanks,
Steve

 

Screen Shot 2019-02-12 at 12.02.20 PM.png

fae_test_chip2z.sv

fae_test_chip2z.xdc

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Hi @stfarley,

The block design is not set up correctly. I would suggest to start fresh using the tutorial linked above. Also make sure to be using the Digilent board files. The Digilent board files correctly configure the Zynq processor and become the default setting.

thank you,

Jon 

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OK I will look at that.

BTW The DMA Example project has the same issue. I pretty much cloned this from it with the addition of the Axi Stuff.

 

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Thanks for your help @jpeyron

I tried the getting started tutorial as well. It doesn't work either. -- If I let it negotiate the link speed I get 1000 and it indicates that the link is up. However the Board never appears as a client on my router, And it is not reachable.

If I build the the peripheral test for the tutorial design I get "Error Setting phy loopback" when I attempt to run it.

 

Edited by stfarley

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Hi @stfarley,

 

1) Are you using the LWIP Echo server application in SDK?  I attached a screen shot of the LWIP echo server application.

2) Please attach a screen shot of your serial terminal when running the Echo Server application ad connected to a COM Port.

3) Are you using a serial terminal like Tera Term? 

4) are you using the Digilent board files? 

5) does you block design look like the below attached screen shot

thank you,

Jon

zybo_z7_20_ethernet_1.png

zybo_z7_20_ethernet_2.jpg

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Hi @jpeyron

1) I am running the LWIP echo server.

2) Here is the terminal screen

-----lwIP TCP echo server ------

TCP packets sent to port 6001 will be echoed back

Start PHY autonegotiation

Waiting for PHY to complete autonegotiation.

autonegotiation complete

link speed for phy address 1: 1000

DHCP Timeout

Configuring default IP of 192.168.1.10

Board IP: 192.168.1.10

Netmask : 255.255.255.0

Gateway : 192.168.1.1

TCP echo server started @ port 7

3) I am attempting to telnet to it with ZOC (From a mac).

Connecting to 192.168.1.10:7 (press Esc to cancel)...

[TELNET] FAIL:

4) I am using the Digilent board files for this test (Although not for my main design as the end target for that design is custom hardware)

5) Yes the block diagram looks like that.

 

A couple of questions.

1) Should the Xilinx peripheral test pass?

2) Should I be able to ping the echo server?

Thanks,

Steve 

 

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Hi @jpeyron

After much experimentation it appears that the issue has to do with either data communications between the MAC and the PHY or a software issue in 2018.3. (Note this is all with the basic build from the getting started guide using the ZyboZ7-20 Board file).

What I have found

1) The control link to the PHY works properly.

    I can change the bit rate by manually setting the link speed and the LEDS on the remote side show the change.

2) The protocol stack is not communicating with remote

     DHCP doesn't work regardless of what speed is selected, Telnet doesn't work with the echo app and the router never sees the ZyboZ7 as a client connection.

3) It appears that the may be a Xilinx support issue with the Peripheral test not working with the Realtek PHY so perhaps that is a just something to ignore.

Is there a board self test that I can run to verify that the hardware is good?

       (Update -- I downloaded the petalinux project BSP. The pre-built image from that works properly so my hardware is OK)

 

 

 

Edited by stfarley

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Hi @stfarley,

Thank you for the update on your hardware. Glad to hear that the Petalinux project works.  I will try getting an zynq/ethernet project going with Vivado 2018.3 and see if I get the same results.

thank you,

Jon

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