I am using the ZyboZ7 to test a prototype a design in Vivado 2018.3. I have everything working but ethernet. What I can't quite figure out is the connections for CLK125, Rest and Interrupt.
The ref guide shows Reset as a zynq output and CLK125 as an input in Fig 5.1, but both as bidirectional Figure 10.1. If I load up the DMA example design the pins identified for these have no connections.
If I bring up my design in SDK and generate the Peripheral test it stalls on the ethernet interrupt test.
I am just wondering how these signals are supposed to be connected.
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stfarley
Hi,
I am using the ZyboZ7 to test a prototype a design in Vivado 2018.3. I have everything working but ethernet. What I can't quite figure out is the connections for CLK125, Rest and Interrupt.
The ref guide shows Reset as a zynq output and CLK125 as an input in Fig 5.1, but both as bidirectional Figure 10.1. If I load up the DMA example design the pins identified for these have no connections.
If I bring up my design in SDK and generate the Peripheral test it stalls on the ethernet interrupt test.
I am just wondering how these signals are supposed to be connected.
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