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No debug cores, when trying to use ILA


I am using the Basys3 version C.

I am trying to learn to use Vivado's Integrated Logic Analyzer (ILA).

But I keep getting a message as if the clock source is not seen by the ILA.

I tried to get assistance with this issue on the Xilinx forum, but so far we haven't been able to make progress on resolving this issue.

Here is a link to that: https://forums.xilinx.com/t5/Design-Tools-Others/Message-No-debug-cores-when-trying-to-use-ILA/m-p/936602#M13274

I was wandering, being that this here is Digilent forum, perhaps someone has been successful in using the ILA on Basys3 ?







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Hi @dag1,

I do not have much experience using the ILA. I did find a tutorial here that looks to be helpful.  I would also look at the Integrated Logic Analyzer v6.1 LogiCORE IP Product Guide

1) Looking at you xilinx forum thread your errors are because the XDC pin name for the clk is uppercase "CLK100MHZ" but in the  VHDL entity main it is lower case "clk100mhz".

thank you,


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