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Basys 3 MicroBlaze project with external QSPI


jrmclaugh

Question

Hello,

I've followed the instructions here:
https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start
to get a basic Microblaze project functioning.  I can successfully program the device with the basic project (although had to figure out the UART bit since that doesn't seem to be on there).

Now I'm trying to add QSPI interface that can connect to the JA Pmod connector but can't seem to figure it out.  I have an ADC that implements an SPI interface with 4 data outputs that should work with a QSPI interface.

I can add the "axi_quad_api" IP to my diagram and it connects most pieces properly.  It can't find outputs to connect to.  I tried renaming the output connection to "ja" (from "SPI_0_0") to use what I found in the "board.xml" file, but I still get the same "IO placement is infeasible" error.

Is it possible to do what I'm trying to do?
If so, does anyone know what I'm doing wrong?
Or at least know where I can look for a description of this kind of process (adding any IP, connecting to any output pins)?

Thanks!

P.S. I am also OK simplifying the initial process to just use standard SPI to figure out the flow of adding IP and connecting it up, then later updating it to QSPI.

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Hi @jrmclaugh,

The ports constrained on the board tab I.E JA, JB.. are made to work with the Digilent IP Cores found here and the board files. 

1) What ADC is being used? What version of Vivado are you using?

2) You can use one of the Digilent IP Cores from the vivado library here and alter it to work with your ADC. You should only need to alter the PmodXXXX.c, PmodXXXX.h and main.c of the IP driver.

3) You can also use the standard AXI QUAD SPI IP core. You will need to right click on the out bus and select "make external" on the T pins. Once you are done with the block design and have created a wrapper you will then create and XDC and constrain the pins you would like to use with the pin names used in the wrapper. 

4) If you have completed Verilog or VHDL code for the ADC then you can also use the "add a module" function in the block design.  Here is a forum thread that discusses using the "add a module" function.

thank you,

Jon

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Excellent list of options, thanks!

1) It is the TI ADS9110, or similarly interfaced TI parts.  The multiSPI interface has a lot of options, but increasing the data bits to 4 should reduce the SPI frequency enough to get us what we need.  Unless I'm misunderstanding, this is a version of QSPI.

2) I dug around these files but it wasn't clear to me what to modify and how to achieve what I was attempting.

3) I had done half of this option (Make External), but couldn't figure out where to constrain the pins.  I found how to here: https://forums.xilinx.com/t5/Design-Entry/Need-help-connecting-pin-constraints-XDC-file-ports-to-Block/td-p/845186  This seems like the most straight forward to me, at least just while prototyping (obviously using a real board constraints file for more production level stuff).

4) We don't have an existing IP core to talk to this module.  We may still end up going this route.  I was just trying to use this method basically just make a custom MCU with an interface to this ADC in as simple a way as possible.

 

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Hi @jrmclaugh,

To use the AXI QSPI IP Core:

1) Once you are done with the block design and have generated a wrapper file, open it and find the names used for the pins you want to constrain.

2) create an XDC file and copy/paste the master xdc from here

3)  Constrain the T pins to the Pins you desire in the xdc. So lets say the names for the T pins in the wrapper are DOUT and you are wanting to use the Pmod Port JA. Here would be what you do to the master xdc:

#Pmod Header JA
#Sch name = JA1
set_property PACKAGE_PIN J1 [get_ports {DOUT[0]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[0]}]
#Sch name = JA2
set_property PACKAGE_PIN L2 [get_ports {DOUT[1]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[1]}]
#Sch name = JA3
set_property PACKAGE_PIN J2 [get_ports {DOUT[2]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[2]}]
#Sch name = JA4
set_property PACKAGE_PIN G2 [get_ports {DOUT[3]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[3]}]
#Sch name = JA7
set_property PACKAGE_PIN H1 [get_ports {DOUT[4]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[4]}]
#Sch name = JA8
set_property PACKAGE_PIN K2 [get_ports {DOUT[5]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[5]}]
#Sch name = JA9
set_property PACKAGE_PIN H2 [get_ports {DOUT[6]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[6]}]
#Sch name = JA10
set_property PACKAGE_PIN G3 [get_ports {DOUT[7]}]
	set_property IOSTANDARD LVCMOS33 [get_ports {DOUT[7]}]

then you should be able to generate a bitstream without issue. If you are still having issues generating a bitstream please attach a screen shot of your block design and wrapper, XDC files. 

thank you,

Jon

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