Missing step in Microblaze SPI Flash guide

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I noticed a very important step that's missing in this guide:

The Quad SPI Core has to be configured in Standard mode. It is configured in Quad mode by default, which causes the bootloader to fail to read the flash. This was frustrating because I'm not an advanced Vivado user and I had no idea how to troubleshoot this at first. I read something similar on a forum, so I reconfigured the SPI Core and it worked. I used a Nexys 4 DDR, if that's relevant.

My suggestion is to add this at the beginning of the guide.


Thank you.


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Hi @stelian,

Welcome to the forums. We have seen customers recently start using the standard mode in the QUAD SPI FLASH IP Core in conjunction with boards that do not have the DDR and uses cell ram like the Nexys 4 and Cmod A7.   If you are changing the mode to standard are you also constraining(XDC) the board with SPIx1.You can also compress your project(Inside of the Bitstream settings check the -bin_file box), set the speed to 33  and select spix1. Then comment out the #define VERBOSE in the srec_spi_bootloader application in the bootloader.c. Compressing the bitstream and commenting out Verbose should easily make up for using a slower transfer process.



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We haven't been able to reproduce your issue.

We added a Quad SPI in Vivado block design 2017.4 and 2018.2 and the default is standard.

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