Missing step in Microblaze SPI Flash guide

[stelian]

Hello,

I noticed a very important step that's missing in this guide: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start

The Quad SPI Core has to be configured in Standard mode. It is configured in Quad mode by default, which causes the bootloader to fail to read the flash. This was frustrating because I'm not an advanced Vivado user and I had no idea how to troubleshoot this at first. I read something similar on a forum, so I reconfigured the SPI Core and it worked. I used a Nexys 4 DDR, if that's relevant.

My suggestion is to add this at the beginning of the guide.

 

Thank you.

 

[JColvin]

Hi @stelian,

Thank you for the feedback; we have passed this information on to our content team to verify and implement your suggestion.

Thanks,
JColvin

[jpeyron]

Hi @stelian,

Welcome to the forums. We have seen customers recently start using the standard mode in the QUAD SPI FLASH IP Core in conjunction with boards that do not have the DDR and uses cell ram like the Nexys 4 and Cmod A7.   If you are changing the mode to standard are you also constraining(XDC) the board with SPIx1.You can also compress your project(Inside of the Bitstream settings check the -bin_file box), set the speed to 33  and select spix1. Then comment out the #define VERBOSE in the srec_spi_bootloader application in the bootloader.c. Compressing the bitstream and commenting out Verbose should easily make up for using a slower transfer process.

cheers,

Jon

[vicentiu]

We haven't been able to reproduce your issue.

We added a Quad SPI in Vivado block design 2017.4 and 2018.2 and the default is standard.

[kb5pgy]

There is a missing step. How do you set up the DDR IP, specifically the "device_temp_i[11:0] input? The tutorial assumes you have a sample project, but where is the sample project? I cannot generate the bitfile, and doing the verification step leads to the following critical error: 

[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /mig_7series_0/device_temp_i

 

[Ana-Maria Balas]

Hello @kb5pgy,

As it says at the begging of the tutorial, it assumes that you already have a Microblaze system built complete with Quad SPI, External Memory, and Uart cores, meaning you already know how to configure the MIG IP (which is used for DDR memory).

I understand that you don't know how to add and configure the MIG IP. This tutorial explains how to create a project which contains Quad SPI IP, MIG IP (for external memory) and AXI UART IP. This is an example project which you can use it to learn how to configure the MIG and then you can follow the How To Store Your SDK Project in SPI Flash tutorial.

Thank you for your input! We will try to change some things in order to clarify the misunderstandings.

Please let us know if there is anything else that we can help you with!

Best regards,

Ana-Maria

 

[kb5pgy]

Thanks. I was able to create an application with Quad-SPI and MIG 7 implemented, but I need to know what the FLASH_IMAGE_BASEADDR value is. I tried 0x00600000 to no avail. I first thought I had bricked it, but that was fortunately not the case.

 

[Ana-Maria Balas]

14 minutes ago, kb5pgy said:

Thanks. I was able to create an application with Quad-SPI and MIG 7 implemented, but I need to know what the FLASH_IMAGE_BASEADDR value is. I tried 0x00600000 to no avail. I first thought I had bricked it, but that was fortunately not the case.

 

Which board do you have? In the tutorial it says the base address:

[kb5pgy]

Mine is the Arty S7-50. I was guessing on the offset value since it wasn't mentioned in the tutorial.

[Ana-Maria Balas]

Could you try address 0x00220000 ?  Or a little bigger like try to increase it with 64 KB each time: 0x00230000, 0x240000... if it still doesn't work, but not too much. Because in the reference manual is says that almost 13.92 MB can remain free to store additional data.

[kb5pgy]

I found another issue. The bootloader is loaded upon reset, but when I attempt to create the linker script for the user application (step 2.3), the pop-up dialog does not allow me to put the code segment in the DDR. It is not an option for the "Place Code Section In:" pull down menu. It has to be a misconfiguration on my part in either the MicroBlaze or the MIG 7.

[Ana-Maria Balas]

I assume you followed the Getting Started with Microblaze tutorial step by step. Did you update the linker script? Right click on the project name -> Generate linker script

[kb5pgy]

Affirmative. But, Vivado insists on not allocating DDR 3 memory space for code. Please just send me sample code to figure this out. I work on embedded systems for a living, and this is the most complicated means of trying to make an Arty S7 standalone. I have spent over a month on this.

[kb5pgy]

You can tell my frustration on this. I have followed you procedure to the letter, but I cannot tell you what the issue is. All I can say is that the bootloader is failing at the XIsf_Initialize step.

[Ana-Maria Balas]

I've created a simple project for Arty S7 50 with MIG, Microblaze, QSPI and UART.

ArtyS7-50.zip

Because of the situation from nowadays I don't have an Arty S7-50 board at home, to test the project. You will have to test it. You only have to follow the steps 3. Program FPGA with bootloader , 4. Flashing FPGA, 7. Program Flash with the Offset address 0x00C00000 and Spansion part number S25FL128S from https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start?_ga=2.67248785.1627086571.1591080069-180711290.1584371590

To see what is printed on the Serial console use Baud rate: 9600, 8 bits, no parity