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herve

ADC/DAC higher than 2 MSPs and >= 12 bits (No FMC)?

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Hello everyone,

I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits.
I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)?
I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs.
Thank you!

Regards

H

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Hi @herve,

Digilent does not currently have either a DAC or an ADC that meets the 2 MSPS data rate requirement.   If you are not able to use an FMC in the design then I would suggest to find a IC that meets the data rate needs with SPI communication and build a custom PCB to work with the FPGA development board you are using.  

thank,you,

Jon

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Just thinking aloud... 2 MSPS for a 10 kHz signal seems unusual. E.g. CD audio uses 0.044 MSPS for 15 kHz BW.

Have you double-checked why e.g. a conventional audio codec would be insufficient?

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Hi xc6lx45,

A conventional audio codec will be insufficient because I have to control the delay of my processed signal with a precision of at  least 0.5 us (2 MHz). Which means that if my DAC has a sampling rate lower than 2 MSPs, I could not reach the 0.5 us required!

Thanks!

H

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is this the absolute group delay or the delay uncertainty? The latter you can calibrate out. And I can interpolate mathematically between samples in a way that is indistinguishable from a faster converter, for a bandlimited signal.

Absolute latency, yes, the sample rate sets an obvious limit, but read the converter datasheet carefully (internal processing latency).

Now I'm guessing on what you're trying to achieve: note that sampling rate has nothing to do at all with time-of-arrival estimation error (theoretical limit: the so-called "Cramér-Rao" bound. It depends solely on the spectral shape and some signal-to-noise ratio).

 

Edited by xc6lx45

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This is the absolute group delay and not the delay uncertainty. If it was the delay uncertainty, yes I could mitigate it by interpolating the samples.
Thank you.

H

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Hi herve,

It is not clear what are you expecting to hear. Are you looking for a commercial module with firmware or just an option for your own design?

There are a number of ICs from Analog Devices, TI, Maxim that satisfy your sampling rate requirements and resolution, for a example, ADC chips LTC2313, LTC2314. However, they require high frequency (>=40MHz) clock, thus, high frequency connector to the FPGA board. Personally, I think Avnet MicroZed board would be a good base for your design. Another option is to look at evaluation boards from ADC, DAC chip vendors. Typically, they are very good for learning capabilities of the product and recognizing gap we need to fill.

Take a look at the Red Pitaya package. It might be overkill but has everything you might need.

Good luck!

Edited by Notarobot
afterthought

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@herve

As far as a board with ADC and DAC devices meeting your sampling and bandwidth requirements look at Terasic ( they are Intel FPGA based ).

As to actual ADC and DAC devices meeting your delay requirements this is tricky ( you'll have to run through the data sheets for the devices on the Terasic boards if they look promising ). I don't know of any converter boards that I feel comfortable recommending that you can easily ( or with some difficulty ) connect to your FPGA platform. The ADC spec. game is challenging even for seasoned engineers. You probably want to look at flash or pipeline architecture ADCs. The current output DACs tend to have the least delay. Once you've figured out what components you want to use there's the analog end to consider. Usually ADCs need a good driver amplifier to get performance and if you use a current output DAC you will probably have to use an OP AMP to get a voltage of the desired span. These all will have a deleterious effect on delay on both ends. There is no easy answer for your question.

[edit] If you need to do any processing such as frequency filtering on the ADC or DAC sides this will also of course affect both data and group delay but you will have some control over this.

 

Edited by zygot

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7 hours ago, Notarobot said:

Take a look at the Red Pitaya package

Oh that! I had such high hopes. This board started out as an open source hardware/software platform and now is something else. The hardware design is not available and calling the software open-source is probably a stretch. But the board is so close to being useful that I still check it out every few years as a possibility.... perhaps one day the company that controls this will go back to the project roots.

Edited by zygot

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Hi zygot,

I have to agree with you that lack of full schematic irritates, however, it's still possible to utilize it for one time projects. Besides, they provide a partial schematic covering ADC interfaces.

Also, it might be possible to accomplish whatever the poster wants by using available software resources. I am not sure that he needs any HW design but configuration.

I have this thing (14 bit version) and use it in my work mostly for measurements and as a signal source. Its ADC and DAC are excellent. My point that making custom hardware will triple the cost and development time.

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@Notarobot

Hi backatcha!,

I do appreciate the testimonial about your success with the Red Pitaya. Such comment help me assess my judgement about the suitability of unknown products. I've had enough unhappy experiences with investing time and effort into tools that restrict vital information that all I see are red flags when considering new ones. So now I'll have to revisit the product pages again in the future.

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Thank you guys for all your help and assistance.
In the end, I think the best solution would be to design a custom DAC that meets my needs, even if it takes me away for a moment from my main goal.
I also think that if Digilent ever came up with Pmod ADC/DACs with a sample rate greater than 2 MSPs, this could be of interest to many people.

Thanks!

H

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