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Digilent Github Demo


AlGee

Question

Just bought an Arty and have followed Digilent Github Demo instructions and get this:

ERROR: [Board 49-71] The board_part definition was not found for digilentinc.com:arty:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7a35ticsg324-1L.

Any thoughts?

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Hi @Clyde,

You can bring this back by clicking on the folder icon on the left hand side. I've definitely had to ask how to open it back up before as well. I've attached a picture of what I'm referring to.

Let me know if you have any more questions.

Thanks,
JColvin

reopen sdk materials.PNG

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That was it!  I am on my way now and thank you.

One quick question about the SDK, sometimes I loose the project explorer window where I may see the source files and I can't figure out how to get it back.  I have poked around in the menus, but nothing seems to help.

Clyde

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Yes, you are correct. It is the ARTY Z7-10 board. No JB.  HDMI port.  Attached is the block diagram and a screen shot from the output of the implementation showing that the pins are incorrect.

I created the exact same project on my ARTY A7-35T with a Microblaze processor.  Identical source code.  In the A7, the design works. Buttons pressed light up the LEDs and the report to the terminal shows the digital value of the key press(es).

With the Zynq, all I get are the terminal messages.

Clyde

ButtonsAndLEDS_InTheWrongPlace.PNG

forum_2020-04-22.pdf

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Hi @Clyde,

Yes, the board files are up to date.

Could you attach your block design and confirm which FPGA/SoC you are using? If I recall correctly, I believe you are using the Zybo Z7-10 (with Pmod JB unloaded and HDMI ports), though I would like to make sure you are not using the original Zybo (which has a VGA port, but also has a Zynq 7010 SoC). What board does it say you are using when you look in the General Settings in the Settings option on the left hand side of Vivado under Project Manager?

Thanks,
JColvin

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I opened the implemented design and did a file export constraints.  When I look in that file,  the pin assignments are wrong for the LEDS and buttons.

I just reinstalled the board files again, fresh, and no difference.   Are the files on Github up to date?

 

Clyde

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Hi @Clyde,

How are the buttons and LEDs assigned in your block diagram? Presuming your AXI GPIO block is labeled as "axi_gpio_0" on your block diagram, are the buttons from the board tab assigned to the "GPIO" channel and the LEDs assigned to "GPIO2" channel? The code snippet at the end of the Getting Started with Vivado IPI tutorial is setup to presume that orientation. If the buttons and LEDs are switched, you swap the second parameter in the XGpio_DiscreteRead, ..DiscreteWrite, ..SetDataDirection to appropriately match what channel it is on.

Let me know if you have any questions about this.

Thanks,
JColvin

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Ok, Somehow the processor clock was wrong and now is at 33.333 MHz and messages come out the terminal.  However, the reading is always 0x00000003 and no LEDs light up.

To me, it makes me think the pin assignments for the GPIO are incorrect.  Is this supposed to work with buttons 3:0 and LEDs 3:0?

Clyde

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Well, I was able to follow everything and build the hardware and software, program the FPGA and launch the code.  No errors and all indications are that things are just fine, except nothing happens.

As best I can tell, the software is not running.  I added this line to  the main   xil_printf ("\rSign on, software running."); 

and nothing comes out of the terminal interface.

Yes,  I did include the bitstream when exporting the hardware, and the FPGA programmed light does come on.  

With no experience with the debugger, I hit suspend and it looks like the uart is stuck trying to transmit the first character.

I am very close.  What could I have overlooked?

Thanks.

Clyde

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Hi @Clyde,

Digilent doesn't have a demo using Microblaze on the Zybo (since it already has an ARM processor built in), but if you follow the Getting Started with Vivado IP Integrator guide, it will set up exactly what you are asking about.

With regards to the ports vs channels, it's one of those nomenclature things. Xilinx for their part calls each collection of outputs that can be configured on an AXI GPIO IP a channel and refers to the individual sets of pins (input pins, output pins, tristate pins) as ports. The AXI GPIO v2.0 LogiCORE IP Product Guide (only 34 pages so it's fairly short) will be a good example showing Xilinx's naming convention which we at Digilent try to match to help prevent confusion.

Let me know if you have any questions about this.

Thanks,
JColvin

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Does an example like this exist for either the Arty or Zbyo with the Microblaze processor?  I have been struggling to find an example of reading from the buttons and writing to the LEDs.  I have the terminal Hello World running, it is the GPIO calls I am stumbling with.

In the reading, there is talk about "channels".  Is this because the GPIO  IP block may have two ports?  If so, why not just call them ports?

Clyde

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Before anyone spends time on the last problem it is now solved

Started up Administrator: Windows PowerShell, navigated to here:
C:\Xilinx\Vivado\2018.2\data\xicom\cable_drivers\nt64
and entered this:
install_drivers_wrapper.bat

I now have a serial port connected to the Arty

 

Success, kwilber's demo has uploaded and is doing things with the LEDs on the Arty. Time for a celebration cup of tea

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Now having problems with the Arty A7-35T's serial port

 

Tried reinstalling, re-booting and tried this that I found online: C:\Xilinx\Vivado\2018.2\data\xicom\cable_drivers\nt64\digilent\install_digilent.exe

All to no avail.

The serial port was working Monday when I first powered up the card and ran the built in tests

 

image.png

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@AlGee,

When you said...

2 hours ago, AlGee said:

I get as far as 'choose the target device'... but the Arty is not in the list?

... what step in the demo I linked were you attempting? I do not see that prompt in any of the steps of the demo.

Could you provide screen shots showing the Vivado project manager and the error?

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Hi @AlGee,

There is two ways to install board files. 

1) First is to install the Digilent board files contents in a folder in a specific path for each version of vivado you download.

2) Second is to add a init.tcl file in a certain folder and all versions of vivado will look there for additional board files. 

Here is a forum thread that shows where and how. I have also attached screen shots that should be helpful as well.

thank you,

Jon

image.png.d4f0b2b43ad592cb4429d228455b4248.png

ini.t_tcl_path.jpg

ini.t_tcl_path_1.jpg

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"And it contains one line: 'set_param board.repoPaths

For some reason I can't past the full line in here?

after repoPaths there is an open bracket the list "C:/Xilinx-work/vivado-boards/new/board_files"then a close bracket

 

 

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OK, I'll stick with Windows.

I've followed the instructions that kwilber suggested... but still no luck

I now have Vivado 2018.2 installed and working
Board Files here: 'C:\Xilinx-work\vivado-boards\new\board_files'
I've put 'Vivado_init.tcl' here: 'C:/Xilinx/Vivado'
And it contains one line: 'set_param board.repoPaths

  1. '
    I get as far as 'choose the target device'... but the Arty is not in the list?
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Hi @AlGee,

Vivado projects  with Microblaze/IP's can be difficult to get to working in a different versions than the project they were made in.  If the project is in VHDL or Verilog then use the version of vivado you would like to use. Then copy the source and constraint files into your project and generate a bitstream.  

Vivado can be more efficient in Linux . The downside is that it can be difficult to install Vivado in linux.  For a new user I typically suggest using windows initially. 

thank you,

Jon

 

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@AlGee,

If you are at all interested in Verilog design, then this tutorial is where I would recommend starting.  You might even find other topics of interest on the associated blog as well, depending on what you are interested in doing.  (Yes, that is a shameless plug.)  If you want an example design, here's one I've put together for the Arty.  The documentation describes getting the memory up and running, should you wish to interact with it from Verilog. (The flash controller still has issues since Digilent swapped flash chips though ...)

Welcome to a fun journey!  :D

Dan

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We have all been in the same place as you are when first starting to work with fpgas. Don't get discouraged, once you get familiar with the process and the tools, things will get easier and more enjoyable. You will find the Digilent community on the forum is always willing to help.

The GPIO demo from the Arty resource page is a good one to try first.

The demo was recently updated for Vivado 2018.2 so you will want to download and install that version. You will also need to install the Digilent board files. Instructions for installing both are described here. Once those are installed, you should be able to download the demo and follow the instructions.

 

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Hi Jpeyron or whoever can help,

Might be best if I delete everything and start again.

A few days ago I received a brand new Digilent ARTY Artix-7 35T Evaluation Kit (and tools voucher)

What version of Vivado should I install?

What tutorial Example Projects will work with it?

Any suggestions ideas to get it do do something will be greatly appreciated,

I have a dual boot PC with Windows 10 or Ubuntu 14.04

AlGee

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Hi Jpeyron

Thank you for the reply.

I'm following the tutorial on:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start

I'm using Vivado 2018.3 - tutorial states: Vivado 2016.4 is used in this tutorial - is this a show stopper?

I've now downloaded and installed Arty board files from here:
https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1
and put them here:
C:\Xilinx\Vivado\2018.3\data\boards\board_files

I now get a lot further as far as:

## create_root_design ""
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:clk_wiz:5.2
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 clk_wiz_1 "
    (procedure "create_root_design" line 113)

I'll try some of the other tutorials - see if I make any progress....
    invoked from within
"create_root_design """
    (file "../src/bd/system.tcl" line 898)

    while executing
"source $origin_dir/src/bd/system.tcl"
    (file "./create_project.tcl" line 103)
update_compile_order -fileset sources_1
set_property location {1 170 140} [get_bd_cells axi_mem_intercon]

So I guess I have other stuff that is missing. I really didn't think it was going to be this difficult just to get started.

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