Vivado IP Interator SDK issue

[Hakob]

Hi All,

I am beginner in FPGA world.

I am trying to learn how to work with Vivado IP Integrator.

When i try to launch my firstProj on Launch on Hardware(System Debugger) I am getting a such kind of issue:

 

make all
Building file: ../main.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"main.o" -I../../firstproj_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"main.d" -MT"main.o" -o "main.o" "../main.c"
Finished building: ../main.c
 
Building target: firstproj.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../firstproj_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "firstproj.elf"  ./main.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
/opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: firstproj.elf section `.heap' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem'
makefile:35: recipe for target 'firstproj.elf' failed
/opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 1168 bytes
collect2: error: ld returned 1 exit status
make: *** [firstproj.elf] Error 1

19:49:21 Build Finished (took 335ms)

 

I try to search on google but cannot to find an answer.

Can someone help to understand the reason?

I am thiinking that this may be some tool setup issue.

 

Thanks!

[jpeyron]

Hi @Hakob,

Welcome to the forums!

1) My first thought is to make sure the Mode Jumper is set to JTAG and not SD.

2) What Development Board are you using?

3) Please post a screen shot of the Vivado block design and the SDK console text.

thank you,

Jon

[Hakob]

HI Jon,

 

Thank you for reply.

Regarding 1) How can I check that?

2) I am using Digilent ArtyA7-35 board

3) attached please find 2 snapshoots of pictures.

 

Thanks,

Hakob

[jpeyron]

Hi @Hakob,

Here is the Arty-A7 resource center. In the section 4 FPGA Configuration of the reference manual here it shows how to set the Mode Jumper JP1.

From the screen shots it looks like your PC's OS is Linux.  The cable drivers do not get automatically installed in linux when you install Vivado.

1) Here is a xilinx AR showing how install the xilinx/digilent cable drivers. If you have not already. Make sure to be root.

2) Make sure that you have added yourself to the dialout group. Here is a forum thread that shows how to add yourself to the dialout group.

3) Please download Adept 2 here.

                    a) Use Adept 2 from the command line with the command "djtgcfg enum" . What is the terminal text response?

4) Were you root when you installed Vivado?

thank you,

Jon

thank you,

Jon

[Hakob]

Thanks Jon, 

I have found the reason of this issue,  the size of micro blaze memory was not enough for my firstproj.elf file, so i have changed the memory space and the issue was resolved.

Thanks for your time and suggestions, I'll look on them also.