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Creating a SPI Frame signal synchronized to SCLK


Bobby Compton

Question

Analog Discovery is a nice tool to use to emulate MASTER SPI and debug.  I have some students who are trying to use it to emulate a SPI Master Device to interface to a peripheral resolver chip from Analog Devices before they implement the design in an FPGA.   The Analog Devices chip has !WR/!FRAME sync signal in addition to the the main SPI.    Is there any easy way for them to use the SPI protocal MASTER mode (using the setup on the SPI MASTER tab) at the same time with generating a pattern signal for !WR/!FRAME that is in sync with SCLK?   If so, how could they reference the frame signal to the SCLK signal from the protocol?

I know the SPI protocol takes control of the pattern generator, but I am not sure how to explain to students to use both modes of operation (SPI Master Mode setup alongside a separate signal sync'd to SPI)?  Attached is the Analog Devices SPI timing diagram we are trying to emulate.

SPI.PNG

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Hi @Bobby Compton

In the Protocol/SPI with Master and Custom, the Select signal is controlled by software, it has no tight timing relative to CLK and SDO signals. The setup/hold for CS to CLK/SDO is about 1/20 milliseconds. 

image.thumb.png.f74f253f2a1103fdd691c90d18659d4e.png

 

The Protocol/SPI with Sensor mode packs all the commands of the loop function, Start/Stop/Read/Write executes with tight timing.

image.thumb.png.e7e869bedd0a418fb7238aaeddedb999.png

 

You can also use the Patterns to generate SPI signals:

image.thumb.png.eb808e5c851dc54cd1867310edc9034b.png

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How would I apply this sensor-mode for SPI when writing a python-script with SDK ?

This long delay between SPI-Select and SPI-CLK/MOSI cannot be used in my application. I need tight timing between the SPI-Select and SPI-CLK/Data.

Can you provide an python example ?

Thanks

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