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CoolRunner-II Starter 2: EPP pin assignment



I'm talking about the CoolRunner-II CPLD Starter Kit Revision 3.0. Poking around with the Adept 2 SDK, the board reports JTAG, EPP and SPI capability. The schematic print also shows 12 I/O lines running between the on-board programmer IC and the CPLD, matching the number of EPP data and control signals (DB0-7, WRITE, ASTB, DSTB, WAIT). A sort of interface between the CPLD and the programmer IC is also hinted at in the Reference Manual, although the bus width is stated as 14 wide there.

From that, I'm guessing there is a way to exchange data between the CPLD and a PC via the Adept "Digital Asynchronous Parallel Interface (DEPP)". Unfortunately, the parallel interface isn't described in more detail in the RM, and "blind" testing bears the risk of a hard short between the programmer IC and the CPLD, as the WAIT control line needs to be pulled low for the transmission to start.

Is there any more information available on the pin assignments of the parallel interface?

[DMGR] Version 2.8.6
[DEPP] Version 2.8.6
[DMGR] Found 1 device(s)
[DMGR] Checking device 0: Cr2s2
[DMGR] "CoolRunner 2 Starter 2"
[DMGR] Product ID 00900126h
[DMGR] Firmware version 011Ah = 282
[DMGR] Device 0 capabilities: JTAG EPP SPI
[DMGR] Device 0 opened at hif=1
[DEPP] Device 0 reporting EPP port count: 1
[DEPP] Device 0 EPP port 0 properties: 0000h
[DEPP] Device 0 port 0 enabled
[DEPP] Could not send data
       ercEppAddressTimeout: EPP timeout occured on Address stage.
[DEPP] Device 0 port 0 disabled
[DEPP] Device 0 hif=1 closed

(EPP throws timeout, because WAIT never gets pulled low by the PLD for the handshake.)

WRITE seems to be on P41@CPLD/"U-PC6". I assume DB0-7 would be "U-PD0" through "U-PD7"?

Best regards,

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Hi @inselcontroller,

That is accurate that DB0-7 is U-PD0 through U-PD7 on the Coolrunner II. Did you configure the Coolrunner II with a DEPP compatible design? This is described more in the DEPP Programmer's Reference Manual and the Digilent Asynchronous Parallel Interface (DEPP) documents that are part of Adept SDK, available for download on the right-hand-side on the Adept Resource Center. Within there, there is also a sample VHDL file for the DEPP that can be used to configure the CPLD so that it properly communicates with Adept on your computer.

I also found what seems to be a complete .ucf file for the Coolrunner II on this users GitHub here which more directly answers your question about the pin assignments under the section called "Parallel Data Bus from microcontroller - Port "C" ", starting around line 297. Specifically, it looks like the pins you need are as follows:

Wait is on P42, Write is on P41, Data Strobe (DSTB) is on P40, and Address Strobe (ASTB) is on P35.

The .ucf and the VHDL file don't have matching names though, so you'll need to fix those as needed so they match.

Let me know if you have any questions about this.


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Hello @JColvin,

the UCF template from the GitHub Gist is exactly what I needed - thank you!

For my rudimentary test setup, I just used edge detectors on what I presumed to be the control lines to show signal transitions via the LEDs. I did see the demo sources for EPP in the Adept SDK folders, however without a working UCF I didn't want to risk mis-configuring the WAIT line to drive against one of the programmer IC outputs.

Thanks again!

Best regards,

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