I'm working with the CMOD S7 development board, which contains a Spartan-7 FPGA, including XADC (Two ADCs, each capable for 1Msps) and two "breadboardable" external analog inputs.
After extensively studying the 92 pages of the UG480 I suppose, that it is not possible, to run the CMOD S7 in simultaneous sampling mode (ADC A and ADC B, both together with 1MSps) by using both external analog inputs, because they are assigned to auxiliary analog inputs no. 5 and 12. Is that right?
"Simultaneous Sampling Mode" (p. 60 on UG480) samples a combination of Ch 0 and 8, 1 and 9, 2 and 10, ... 4 and 12, 5 and 13, ... at the same time. To cover 5 and 12, it is necessary to select 4 and 12 and 5 and 13, what results in two sampling periods per sequence, what leads to 500 kSps.
Is there a trick to enable 2x 1MSps anyway in that situation, for ADC channel 5 and 12 ?
If not, why did Digilent choose ADC channel 5 and 12 as external inputs on the CMOD S7, what reduces the potential of that board...?
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TestDeveloper
Hello Community,
I'm working with the CMOD S7 development board, which contains a Spartan-7 FPGA, including XADC (Two ADCs, each capable for 1Msps) and two "breadboardable" external analog inputs.
After extensively studying the 92 pages of the UG480 I suppose, that it is not possible, to run the CMOD S7 in simultaneous sampling mode (ADC A and ADC B, both together with 1MSps) by using both external analog inputs, because they are assigned to auxiliary analog inputs no. 5 and 12. Is that right?
"Simultaneous Sampling Mode" (p. 60 on UG480) samples a combination of Ch 0 and 8, 1 and 9, 2 and 10, ... 4 and 12, 5 and 13, ... at the same time. To cover 5 and 12, it is necessary to select 4 and 12 and 5 and 13, what results in two sampling periods per sequence, what leads to 500 kSps.
Is there a trick to enable 2x 1MSps anyway in that situation, for ADC channel 5 and 12 ?
If not, why did Digilent choose ADC channel 5 and 12 as external inputs on the CMOD S7, what reduces the potential of that board...?
Arthur
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