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NexysDDR reference design

pierre antony

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pierre antony Newbie

pierre antony

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Hello,

I have built this reference design with Vivado 2015.4.

https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start

Where creating the bitstream, I get the following error:

Vivado Commands

apply_bd_automation -rule xilinx.com:bd_rule:mig_7series -config {Board_Interface "DDR2_SDRAM" } [get_bd_cells mig_7series_0]

launch_runs impl_1

[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/xit/vlog_synth_rpr.xit': error renaming "c:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/ip/uart_test_bd_mig_7series_0_0/_tmp/uart_test_bd_mig_7series_0_0" to "c:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/ip/uart_test_bd_mig_7series_0_0/uart_test_bd_mig_7series_0_0": permission denied

[IP_Flow 19-167] Failed to deliver one or more file(s).

[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'uart_test_bd_mig_7series_0_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs:

[IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'uart_test_bd_mig_7series_0_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs:

[BD 41-1030] Generation failed for the IP Integrator block mig_7series_0

thanks,

Pierre

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jpeyron Prolific Poster

jpeyron

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Hi @pierre antony,

 

Here is a completed Vivado 2015.4 Nexys 4 DDR Hello World project.

1) Please add a screen shot of the errors in the Vivado tcl console.

2)  When adding the Microblaze did you select 32 and 16 for the cache?

3)  Did you alter anything in the Microblaze Core?

4) Just to verify, you are using the digilent board files.

thank you,

Jon

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pierre antony Newbie

pierre antony

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HI Jon,

Thanks for the hello world project.

I have errors when I open the BD:

 [IP_Flow 19-479] 'UARTLITE_BOARD_INTERFACE--> UARTLITE_BOARD_INTERFACE' cyclic dependency found while setting value 'usb_uart' on parameter 'UARTLITE_BOARD_INTERFACE'.
 [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart
 [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart
 [IP_Flow 19-3439] Failed to restore IP '/axi_uartlite_0' customization to its previous valid configuration.


This is what I get when I rerun validate design in the BD:

[IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart

[IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart

[IP_Flow 19-3439] Failed to restore IP '/axi_uartlite_0' customization to its previous valid configuration.

[IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart

[IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart

[IP_Flow 19-3439] Failed to restore IP '/axi_uartlite_0' customization to its previous valid configuration.

If I remove AXI UART lite and out it back in the BD, then the errors go away.

I have noticed the clock to the MIG is 100MHz. Now, when I synthesize this project, I have errors:

[Synth 8-439] module 'design_1_mig_7series_0_0' not found ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":573]
[Synth 8-285] failed synthesizing module 'design_1' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":13]
[Synth 8-285] failed synthesizing module 'design_1_wrapper' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v":12]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
 

Concerning my project:

1) Here are the messages:

[Synth 8-439] module 'uart_test_bd_mig_7series_0_0' not found ["C:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/hdl/uart_test_bd.v":1837]
[Synth 8-285] failed synthesizing module 'uart_test_bd' ["C:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/hdl/uart_test_bd.v":1308]
[Synth 8-285] failed synthesizing module 'uart_test_bd_wrapper' ["C:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/hdl/uart_test_bd_wrapper.v":12]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

Good news is that both your project and mine have the same problem with the MIG

2) 16 for the cache as requested in the ref design:

https://reference.digilentinc.com/_media/nexys4-ddr/nexys4ddr-mb_blockauto.png

3) No change in the microblaze other than what is asked in the link:

https://reference.digilentinc.com/_media/nexys4-ddr/nexys4ddr-mb_blockauto.png

4) Yes I am using the digilent board file. I have attached what I use from this link:

https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1

nexys4_ddr.zip

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jpeyron Prolific Poster

jpeyron

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Hi @pierre antony,

Looking at the nexys4_ddr.zip i believe you do not have the board files installed correctly. Please download the board files from here. Then go to C:\Xilinx\Vivado\2015.4\data\boards\board_files and add the contents of the digilent's new folders board files to your board files folder. When you create a project you should be able to select the Nexys 4 DDR like shown in the screen shot below.

thank you,

Jon

Nexys4ddr_2015_4.jpg

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pierre antony Newbie

pierre antony

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Hello Jon,

 

With C1 Nexys4 DDR, it is worse.

I get an error message at step 8.3 of the tutorial:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start

The attached picture shows the error message.

The MIG is not even connected with the board file changes...

Also no improvement when I try to synthesize the project you've sent to me.

[Synth 8-439] module 'design_1_mig_7series_0_0' not found ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":573]

[Synth 8-285] failed synthesizing module 'design_1' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":13]

[Synth 8-285] failed synthesizing module 'design_1_wrapper' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v":12]

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

I am one step behind with C1 version of the board...

What can I do?

withC1board.png

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