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JrV

Artix-7 35T "Arty" FPGA Evaluation Kit

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Hello,

I have ordered the  Artix-7 35T "Arty" FPGA Evaluation Kit to educate FPGA design (VHDL) using Vivado tool.

Today, I am looking for some starting points: tutorials, websites, books, online courses, ...

All help & tips are welcome.

Thanks.

JrV

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My question is similar. I have received my Arty. I have tried to follow the  "Arty - Getting Started with Microblaze" document in your Resource Center but it uses Vivado 2105.1. I have downloaded and installed the current version - Vivado 2016.3 HLS and HLX Webpack which appears to have different navigation. I tried to download Vivado 2015.1 but the Webpack installer for that wanted to install 2016.3.

The voucher that came with Arty provides a license  for "Vivado Design Edition" is that "Vivado HL Design Edition" or something else?

Some help through this naming jungle would be appreciated. I am trying to move up from ISE on Spartan6 which I have been programming for production for some years but not finding it easy.  

Is there some up-to-date documentation?

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@Rockbird,

This may not quite be what you are looking for, but you can find a fairly complete implementation of a ZipCPU on the Arty here.  If nothing else, it proves that you can program a CPU with Verilog.  The design includes such things as:

  • Obviously, a CPU.  The ZipCPU is designed to be a simpler CPU to both build and work with than the Xilinx microblaze CPU.
  • A simplified wishbone bus (not AXI).  Unlike the Microblaze designs, this implementation has only a single bus, rather than the 4 AXI busses containing up to 5 channels each that microblaze uses--each with up to five channels of information!  Ouch.  No, the wishbone bus is a much simpler bus.
  • A fullly featured EQSPI flash controller, that can be used to program the flash, reconfigure devices, and even put programs into memory.
  • An example of how to use the configuration port, so as to reconfigure the FPGA if you'd like.
  • It still uses Xilinx's Memory Interface Generator to generate the DDR3 SDRAM memory interface.  Unlike many other ways of doing MIG, this one shows how to connect a simple wishbone bus to the complicated AXI bus to run the controller--via a fairly simple bridge.  Although my plan has been to replace the MIG controller with an opensource DDR3 SDRAM controller, for now I'm using the MIG AXI interface to the memory.
  • It demonstrates how to build a complete controller for ethernet--both for the packet interface as well as the control interface.
  • It contains a demonstration of how to lock to and track a GPS PPS signal from a PModGPS with subsecond accuracy.
  • I'm also told by others that the source code I'm referencing is well documented.

The biggest thing the design is still missing is a fully featured specification, to include instructions on how to set up the MIG, but ... that could be fixed quickly if someone was interested and needed it.

Dan

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Hi Rockbird,

The tutorials and demos are made to work with Vivado and not Vivado HLS. When you downloaded Vivado 2016.3 the default setting downloads both. Looking at Vivado 2016.3 I haven't seen anything different with the tools as of yet, so following the "Arty - Getting Started with Microblaze" should be the same. The tutorials should still all work without issue on the newer versions. Make sure to install the board files like it describes in the tutorial. Also the "Arty - Getting Started with Microblaze"  tutorial uses Xilinx SDK so make sure you have downloaded(an option when downloading Vivado) this as well and make sure its the same version i.e. 2016.3.  The voucher that came with the Arty provides a license for "Vivado Design Edition" which would give you the design edition for vivado 2015.4 and below. The webpack include everything that is in the design edition from version 2015.4 and up. I just generated bitstream on the vivado part of  "Arty - Getting Started with Microblaze" with no issue. Hope this helps!

thank you,

Jon

arty_esc.jpg

arty_esc1.jpg

arty_ect2.jpg

Edited by jpeyron

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On 14-3-2016 at 7:40 PM, JColvin said:

Hi JrV,

I would recommend checking out the Resource Center that Digilent has created for the Arty.

Let us know if you have any questions!

Thanks,
JColvin

 

Hello,

What is missing is a good tutorial that describes all the aspects of designing with Vivado and SDK,

a tutorial that describes all the aspects in detail.

Regards,

J.

 

 

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Hi J,

I agree that we do not currently have a comprehensive tutorial for designing with Vivado and SDK since (as you likely know) there are a huge range of things to explore. At the moment, the best thing we have (that I personally used) is this getting started with Vivado guide.

Thanks,
JColvin

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Hello,

 

Thanks for the response.

I hope in the future that there will be a couple of tutorials released for designing Vivado and SDK. 

Best regards,

J.

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Hi,

I would like to use ARTY board for Boundary Scan testing using Corelis Tool. But, I have multiple queries listed below.

1. I understand that it has a JTAG cahin connected to FPGA. I see that it has got a USB JTAG interface.But do the board have a provision to connect a custom JTAG Interface cable from Corelsi HW controller?

2. Has anyone used this board for Boundary Scan Testing?

3. Corelis Tool requires 

  • Net List/ Design FIles
  • Schematics
  • BSDL File and
  • Bill of Materials

Will Digilent provide all necessary inputs

If its boundary scan compatible without issues, I am planning to get one. Please help to get above queries answered.

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Hi Nirmal Shyam,

I have asked some of our applications engineers about your inquiries; they will get back to you here on the Forum.

Thank you for your patience,
JColvin

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Hi Nirmal Shyam,

I am not aware of this board being used for boundry scan testing or if it is compatable with the Corelsi HW controller. Unfortunately, i do know that we would not be able to provide you with the net list/design files ,bill of materials or full schematic(part of the schematic is omitted due to it being proprietary in nature). 

thank you,

Jon

Edited by jpeyron

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