How to generate another, faster clock (CMOD S7) ?

[TestDeveloper]

Hello community,

i started to work with vivado some weeks ago and successfully created some verilog based projects for my Digilent CMOD S7 evaluation board.

Now I want to use a faster clock then the board standard 12 MHz (CMOD S7 should work up to 450 MHz, i red in the reference paper).

E.g. I tried to create a 100 MHz clock with the following lines (added the third line "create_generated_clock" to the default constraint file *.xdc):

set_property -dict { PACKAGE_PIN M9    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }];
create_generated_clock -name clk100 -source [get_ports { clk }] -multiply_by 25 -divide_by 3 [get_ports { clk100 }];

I added clk100 as additional input in my top verilog module.
The project is a "plain" verilog HDL project without any IP.

This does not work:

- Synthesis runs fine.
- Implementation creates one critical Warning: "Generated clock ... has no logical paths from master clock ..."
- Generate Bitstream fails with an Error.

Can anyone tell me a solution? Pleas e provide the correct Line I need to fill in in the constraint file (I think, it's just a very simple mistake).
I looked for hours but could not find a clear explanation about this problem.
Thanks for help in advance!

Arthur

[jpeyron]

Hi @TestDeveloper,

If you havent seen Xilinx's UG903 Vivado Design Suite User Guide Using Constraints i would suggest looking at page 82-97.  Here is a forum thread that show how to do this in VHDL, sorry I haven'r found anything in Verilog.  The clocking wizard is a much easier way to accomplish generating different clocks. It is fairly easy to use with verilog/vhdl  as well. Here is a VHDL project that uses the clocking wizard.

thank you,

Jon

[TestDeveloper]

Hi jpeyron,

The advice about the wizard was good, but I'm (still) not a friend of using that Vivando wizards.
Unfortunately, DCM_CLKGEN doesn't work on a 7-Series FPGA (just up to 6).

But, that brought me to another thread:
https://forum.digilentinc.com/topic/5037-clockpll-for-cmod-a7solved/?_fromLogin=1
what bring me to the following solution, that works (12 MHz * 50 / 6 = 100 MHz):

    wire mmcm2_clk_fb, locked_1, clk100;

    MMCME2_BASE #(
        .BANDWIDTH("OPTIMIZED"),
        .CLKFBOUT_MULT_F(50.0),
        .CLKFBOUT_PHASE(0.0),
        .CLKIN1_PERIOD(83.33),
        .CLKOUT0_DIVIDE_F(6.0),
        .CLKOUT0_DUTY_CYCLE(0.5),
        .CLKOUT0_PHASE(0.0),
        .DIVCLK_DIVIDE(1),
        .REF_JITTER1(0.0),
        .STARTUP_WAIT("FALSE")
    )
    MMCME2_BASE_inst (
        .CLKOUT0(clk100),
        .CLKFBOUT(mmcm2_clk_fb),
        .LOCKED(locked_1),
        .CLKIN1(clk),
        .PWRDWN(1'b0),
        .RST(1'b0),
        .CLKFBIN(mmcm2_clk_fb)
    );

So, I was totally wrong with the constraint file. The MMCME2_BASE macro is the right one to use in my verilog file - easy!
Thanks!

[xc6lx45]

I think you can also copy the code from the wizard-generated output file. There may be a project option for the language of generated "output products", check that if you want Verilog and get only VHDL.