How to generate another, faster clock (CMOD S7) ?

[TestDeveloper]

Hello community,

i started to work with vivado some weeks ago and successfully created some verilog based projects for my Digilent CMOD S7 evaluation board.

Now I want to use a faster clock then the board standard 12 MHz (CMOD S7 should work up to 450 MHz, i red in the reference paper).

E.g. I tried to create a 100 MHz clock with the following lines (added the third line "create_generated_clock" to the default constraint file *.xdc):

set_property -dict { PACKAGE_PIN M9    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }];
create_generated_clock -name clk100 -source [get_ports { clk }] -multiply_by 25 -divide_by 3 [get_ports { clk100 }];

I added clk100 as additional input in my top verilog module.
The project is a "plain" verilog HDL project without any IP.

This does not work:

- Synthesis runs fine.
- Implementation creates one critical Warning: "Generated clock ... has no logical paths from master clock ..."
- Generate Bitstream fails with an Error.

Can anyone tell me a solution? Please provide the correct Line I need to fill in in the constraint file (I think, it's just a very simple mistake).
I looked for hours but could not find a clear explanation about this problem.
Thanks for help in advance!

Arthur

 

[xc6lx45]

Hi,

it's not handled through the constraints file. This would tell Vivado that you already have a faster clock and feed it into the chip.

What you should look at is the "clocking wizard". On Vivado main screen, locate "Flow manager" / "PROJECT MANAGER" (left side of screen)

There is an entry "IP catalog". Click it.

Look under "FPGA features and design" for "clocking wizard". Double-click it and a GUI opens.

In "clocking options", set "MMCM" (PLL won't work from 12 MHz input clock). Change "input frequency" from 100 to 12 (MHz). Under "output clock", enter your desired clock frequency.

For a start, you don't need any other ports than "input" and "output" (disable "reset" and "locked").

In your RTL code, feed this block the 12 MHz crystal clock.

 

 

 

[TestDeveloper]

Hi xc6lx45,

thanks for that very detailed and good description, how I could do it with the wizard. I'm sure, that will work.

But, additionally, now I found a way to add the MMCME2_BASE just in my verilog code:

    wire mmcm2_clk_fb, locked_1, clk100;

    MMCME2_BASE #(
        .BANDWIDTH("OPTIMIZED"),
        .CLKFBOUT_MULT_F(50.0),
        .CLKFBOUT_PHASE(0.0),
        .CLKIN1_PERIOD(83.33),
        .CLKOUT0_DIVIDE_F(6.0),
        .CLKOUT0_DUTY_CYCLE(0.5),
        .CLKOUT0_PHASE(0.0),
        .DIVCLK_DIVIDE(1),
        .REF_JITTER1(0.0),
        .STARTUP_WAIT("FALSE")
    )
    MMCME2_BASE_inst (
        .CLKOUT0(clk100),
        .CLKFBOUT(mmcm2_clk_fb),
        .LOCKED(locked_1),
        .CLKIN1(clk),
        .PWRDWN(1'b0),
        .RST(1'b0),
        .CLKFBIN(mmcm2_clk_fb)
    );

what also works. I'm (still) not a friend of using that Vivando wizards and prefer the "good old text code" in my HDL file ;-).

You'r right. I was totally wrong with the constraint file.

[xc6lx45]

Hi,

usually I'm with you on avoiding "wizardry" but there is a risk that you're venturing out into uncharted waters. It's not a trivial subsystem, at least read the manual for the block - just kiddin' it's 114 pages
Or not. Maybe check page 77, the paragraph at the bottom. Myself, I would still use the wizard, if only for the jitter estimate (it can vary greatly, depending on settings).

Also consider LOW instead of OPTIMiZED for improved input jitter rejection, as long as the generated clock phase relative to the input clock does not matter.

And it may help a little to cascade two stages, especially if the clock is meant for something else than driving digital logic.

 

[D@n]

@TestDeveloper,

I instantiate my PLL's and MMCE's like that all the time.  Vivado has been fairly robust in how it handles it, so in spite of the pitfalls it has always worked for me.

One thing you might consider doing is to create a counter that counts down (CLOCK_RATE_HZ/2), and then toggles an LED.  You might find that useful to know that you got the clocking right.

Dan

[TestDeveloper]

Hi Dan,

did it.

reg [25:0] cnt = 0;
always @(posedge clk100) cnt <= cnt + 1;
assign led[0] = cnt[25];

...shows, that clk100 runs wirh around 100 MHz.

Thanks!

Artur