Using Digital Discovery to Bit-Bang Protocols

[algae]

I'm looking for hardware that I can use to bit-bang a custom digital board I'm testing. I see the that one of the WaveForms SDK examples drives some pins and samples some pins. This would allow me to write C code to drive stimulus to my board, sample responses from the board, and respond with more stimulus in an algorithmic way as opposed to the canned pattern generator/logic analyzer combo that I think the Digital Discovery is intended for. So, the question is: what kind of expected data drive/sample rate can I expect using this bit-bang approach with your SDK through the USB port to my host computer? Alternatively, do you guys have a better solution for this short of programming an FPGA to implement my protocol and store stimulus and response data?

Also, can I configure one of the DIO as a free-running, independent clock output while other DIO are used for communication?

[attila]

Hi @algae

To USB transfers have latency of few ms, so a host application with sequential sample and driver will have a rate around 10s ... 100 Hz
For fast response you could use the WaveForms / Pattern Generator / ROM logic: https://reference.digilentinc.com/waveforms_-_rom_logic

The WaveForms / Protocol takes control of the Patterns and Logic Analyzer. It uses these to perform the transfers. You could eventually use the StaticIO to control the unused DIOs in specific protocol.

If you need an FPGA board you can pick up one based on your need, CPL/FPGA/Zynq, size, with or w/o memory, various IO types...
https://store.digilentinc.com/fpga-development-boards-kits-from-digilent/

[algae]

The ROM logic looks like a good way to do this since I can implement an FSM to do the bit-banging and run at a much higher speed. Am I correct that I use the FDwfDigitalOutDataSet API function to load in the ROM pattern memory?

How about the Algorithmic Generator? What can that do and how might I be able to use that from custom code?

[xc6lx45]

Just a thought: If you use a plain FT2232H (e.g. via this module) you can bit-bang one bank of 8 bits at 1 MHz (max. clock rate 500 kHz). It's relatively straightforward to program.

The achievable roundtrip latency "in production" is 125 microseconds or even one third less under lab conditions (because "ping-pong-ping" can be made to fit in one USB 2.0 8 kHz microframe if the PC adds no delay).

 

[algae]

I decided to go with the DD since it can get me the MHz rates that I need.

However, I can't seem to figure out how to use the SDK to implement the ROM  or an FSM. I can generate the outputs and sample inputs, but the docs don't seem to tell me how to route the inputs to the pattern memory address lines. So, how do I go about setting the mux to use the inputs for the pattern memory addressing instead of the counter?

[attila]

Hi @algae

The WaveForms application has an interface to configure the ROM logic with a table.
In the SDK is a bit more complicated, needs some coding, data shifting. Basically the DIOs as inputs are used to address the custom data (ROM). 
You can find an example at:
C:\Program Files (x86)\Digilent\WaveFormsSDK\samples\py\ DigitalOut_ROM_Mux.py