I wanted to write a small shift register Control program in Basys 3 board. It is a very short code and has 2 Inputs one is clock (100 MHz) and the other one is reset and 5 outputs. The program should generate a clock internall by dividing the the 100 MHz by 16. The generated clock should be outputted at two Pins. Beside that for every generated clock period, one bit should be shifted at one another. This bis should be taken from a constant pattern with 8 bits. That is it.
My code you see as attachment. The simulation and synthesis seem fine. Only the implementation produces the following
Could not resolve non-primitive black box cell 'shift_register_ctrl' instantiated as 'uut'. Unisim Transformation Summary:
Black Box Instances: Cell 'uut' of type 'shift_register_ctrl' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
I have some idea about vhdl but not perfect. Obviously there is issue with instantiating the component. There might even be Syntax Errors. Would be very much appreciated if you could look at the look and give me some advices.
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Olonbayar
Hi all digilent guys,
I wanted to write a small shift register Control program in Basys 3 board. It is a very short code and has 2 Inputs one is clock (100 MHz) and the other one is reset and 5 outputs. The program should generate a clock internall by dividing the the 100 MHz by 16. The generated clock should be outputted at two Pins. Beside that for every generated clock period, one bit should be shifted at one another. This bis should be taken from a constant pattern with 8 bits. That is it.
My code you see as attachment. The simulation and synthesis seem fine. Only the implementation produces the following
Could not resolve non-primitive black box cell 'shift_register_ctrl' instantiated as 'uut'. Unisim Transformation Summary:
Black Box Instances: Cell 'uut' of type 'shift_register_ctrl' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
I have some idea about vhdl but not perfect. Obviously there is issue with instantiating the component. There might even be Syntax Errors. Would be very much appreciated if you could look at the look and give me some advices.
cheers Olonbayar
topmodule.vhd
shift_register_ctrl.vhd
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