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Problem loading firmware


zerosmx

Question

I made  a simple design in Vivado for the Zybo 7-20 board. It connects a clock from the PS to pin M17, which should be the RGB LED for Blue. I also included an ILA to check if the logic line would correctly go high.

I generated a bitstream without issue, and exported my hardware + bitstream to XSDK.

Once there I used the hardware export to generate a BSP, and used the BSP to make an FSBL. Then I used a helloworld example to make a program.

I tried the Create Boot Image tool to put the 2 .ELF files and the bitstream into the BOOT image, and marked the FSBL as a (bootloader) in the top slot.

I then put this on a FAT format micro SD card.

Next I changed JP5 to sit on the SD pins, and JP6 to WALL. Then I connected the power supply and a Micro USB.

 

When I turn on the board, the PGOOD light comes on but not DONE.

If I switch JP5 to QSPI, the usual light effects come on.

If I switch JP5 to JTAG, and select Program FPGA from SDK, Digilent Zybo Z7 210351A824DDA/2-xc7z020 shows up as an option for target, and programing claims to succeed. The LD12 lights up, but LD5 and 6 do not, and Vivado is unable to detect the ILA.

 

Can someone recommend how to debug this further?

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Cool, so if I use the SDK to program the FPGA, and then use the SDK to load my program, my LED comes on as expected and the ILA responds, so that works.

 

So the question is why the "BOOT.bin" file on my SD card is not being read.

 

I would assume that the two options are that either my hardware configuration isn't correctly set up to boot from the SD card, or that my FSBL/BOOT.bin are somehow incorrect and causing the boot to fail.

 

As far as I understand it the only hardware configuration necessary is to move JP5 to the two pins marked "SD", so I think that's fine.

 

Should an FSBL generated from XSDK work without me needing to make any changes to it?

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Hello, yes I have the card formatted and placed BOOT.bin in the correct location.

My current suspicion is that the Bootloader is off, since the bitstream and baremetal program both work fine when manually loaded.

 

The tutorial you linked doesn't explain how exactly to create the FSBL, it's just assumed that it already exists, so I'm wondering what steps need to be taken to configure that?

 

Right now, I just created a new application, and selected "Zynq FSBL" as the template. Is there anything else I need to do with that or should it work at that point?

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So after turning on DEBUG mode for the FSBL and attempting to load that onto the board I see this message:

 

Xilinx First Stage Boot Loader

Release 2018.1 Jan 16 2019-06:09:12

DDR_INIT_FAIL

FSBL Status = 0xA007

 

Any idea about what might cause that?

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I've found the solution to my issue.

 

For whatever reason, it seems that the Zynq PS block in my design didn't correctly import whatever settings are linked to the board files, so it wasn't configured for the memory part used on the Zybo.

 

I made a new project and a new PS7, and that got the correct settings, so I exported those into a file, and imported them into my main project. Then everything worked correctly.

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