Reading Data From BRAM of Zybo but receiving data is garbage.

[Abdul Qayyum]

Hi,
I am working on a project in which i need to read the data from BRAM. I give the constant input to BRAM second port and generate the bit stream. After that i Export the Hardware and Import it. In SDK i am reading the data in SDK terminal where i  had written the data on BRAM address.
But Problem is that i am receiving the garbage data instead of that data which i had written on specific address. 
What could be the problem? 
Regards, 
AQ

[Notarobot]

Dear Abdul,

Take a time to describe your project and then you will have better chances to get a useful answer.

[jpeyron]

Hi @Abdul Qayyum,

I would also include the SDK Code that you are using.

thank you,

Jon

[Abdul Qayyum]

Hi @Notarobot

 

I am assigning constant value to Port B of BRAM in block diagram as follow:

web[3:0],  en <- 1

dinb[31:0] <- 12345678

addrb[31:0] <- 1073741824 = 0x40000000

resetb <- 0

further Port A of BRAM is connected with AXI_BRAM_CONT which is connected with ZYNQ

I generated bitstream of this block design and exported it to SDk, where i wrote the code to access the data from 0x40000000 location of BRAM. but its giving me garbage values, instead of  12345678.

 

[Abdul Qayyum]

Hi @jpeyron

Here is the SDK code which i am using.

thank you,

AQ

 

[jpeyron]

Hi @Abdul Qayyum,

On page 41 of this PDF  here is some good SDK code to start from. In the attached code nothing has been placed in 0400c0000. Also  wouldn't you want to use %d instead of %x?

cheers,

Jon

[Notarobot]

Hi, Abdul,

Here are my notes/recommendations:

1. Open your block diagram in Vivado where you created BRAM configuration and then check the address editor. You should see whether the BRAM address was assigned. If you find assigned see axi_bram_ctrl_0 OffsetAdress and the Range then the BRAM was created and mapped to the memory.

2. Writing and reading from BRAM requires a clock signal. Check Xilinx templates for BRAM which you can access inside the Vivado. I am not sure that the code you've used to write into BRAM does anything.

3. You don't use an absolute address in your HDL when BRAM created in Vivado. Vivado maps the address 0x4000_0000 to 0. So you can start from the address 0 and it will be the lowest address of the BRAM. If your don't use Vivado then you will need to define your block in HDL and include addresses, and many other parameters.

4. The C-code in SDK should use BRAM address from the file parameters.h. You just need to use XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR as the begining of the BRAM address space.

5. You can treat BRAM as RAM meaning that all read/write operators are the same.
For example you can copy BRAM content into the RAM:

for(i = 0 ; i < BRAM_SIZE ; i++)
*(destination + i) = *(source + i);
where source = XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR

Disclaimer: always read documentation, whatever you find on Internet might not be correct.

Good luck!

[Abdul Qayyum]

 @Notarobot  @jpeyron thanks for your concern. I reviewed the whole process and found that i was not enabling the enable write pin of BRAM due to which i was receiving the garbage data. 

Regards,

AQ

[jpeyron]

Hi @Abdul Qayyum,

Glad to hear you were able to resolve the issue. Thank you for sharing what you did to resolve the BRAM issue.

thank you,

Jon

[sagar0077]

On 1/17/2019 at 6:07 PM, Abdul Qayyum said:

 @Notarobot  @jpeyron thanks for your concern. I reviewed the whole process and found that i was not enabling the enable write pin of BRAM due to which i was receiving the garbage data. 

Regards,

AQ

can you give me example how can i read BRAM port b data from my custom rtl verilog code