ZYBO peripherals

[SAYALI]

HELLO,

          I am using ZYBO board for my project, So I want  VHDL codes for interfacing of peripherals such as GPIO, TIMER, UART, Memory & LED driver of zybo board. What can I do to get vhdl code for interfacing of peripherals of  zybo board?

[JColvin]

Hi Sayali,

I have asked some of our applications engineers to see if there any convenient materials available for the Zybo; they'll get back to you here on the forum.

Thanks,
JColvin

[artvvb]

Hi Sayali,

I'd recommend running through the ZYBO Create a Custom IP Core tutorial (https://reference.digilentinc.com/zybo:custom_ip_cores). The Xilinx tools will let you instantiate VHDL designs inside of a Verilog project, so in the step 4, "Add user logic here" section, rather than copy-pasting the PWM code, you should be able to design a VHDL equivalent, and instantiate it. While the project wouldn't be pure VHDL - the AXI controllers would be automatically created for you in Verilog - you would be able to have VHDL between this bus and the peripherals. I haven't seen a way to have Vivado create the AXI controller in VHDL, so I'm not sure this is exactly what you are looking for...

Thanks,

Arthur.

[SAYALI]

13 hours ago, artvvb said:

 

 

 

[SAYALI]

Thanks artvvb & Jcolvin,

                   Actually, I want to implement DALI(Digital Addressable Lighting Interface) protocol in ZYBO with help of verilog or vhdl. DALI is the digital serial communication protocol. To implement DALI protocol in Zybo, I want to VHDL or verilog code to interface board peripherals such as GPIO, LED driver, Timer, UART. If any tutorial available about that plzzz send me link.....

 

Regards,

SAYALI

[artvvb]

Hi Sayali,

What do you mean by interfacing with the peripherals? I would assume that either just controlling them from the FPGA side of the ZYBO, or allowing their interaction with the processor side of the ZYBO. If the processor side, then I would look at the getting started guide for ZYBO, https://reference.digilentinc.com/zybo:gsg, which shows how to use Vivado's IP Integrator to control GPIO and UART. The tutorial I linked above shows how to write a custom IP core, allowing you to build your own DALI module. As for a timer, there's an "AXI Timer" block provided by Xilinx in the IP integrator, which is interfaced with through C in the same way as the GPIO in the getting started guide.

Thanks,

Arthur

[SAYALI]

Thanks a lot .....

  I have another daubt about ucf file format. Plz guide about zybo ucf file format..

 

[Bianca]

Hello,

For Vivado you can't find a UCF file, that works only with ISE. You can find the constraints file on Zybo's page here and it's called Master XDC. 

Best regards,

Bianca

[SAYALI]

Thanks Bianca....

I want whole pin configuration file for ZYBO (XC7Z010 and CLG400ACX1437) FPGA BOARD......plzz send me link or tutorial where I will got all pin configuration of zybo board..

[SAYALI]

I want to install vivado in my laptop but I don't have license copy to install this software. plzzz reply... what I have to do to solve this problem... any crack version or free vivado software is available... or not..

 

[Bianca]

Hello Sayali,

To answer your first question. What we had published is the whole XDC pin configuration file for Zybo. Because Zybo is a Zynq board it has the UART connected to the processor. That means that you can configure the UART just using the processor and using the XML file. The MIO pins, all are connected that way. You cannot use the UART just with the FPGA. You can find the XML file here

Regarding the Vivado problem, you can download and install the webpack version which is free. You will find it on Xilinx page here

Best regards,

Bianca

[SAYALI]

Hello,

            I am using VIVADO 2014.2 software. I have counter code in verilog. I imported ise file after synthesis is done, then I add xdc file through add source. I clicked on run implementation. At that time, design implementation sucessfully created. but I found error while generating bitfile. plz .... help guys...I attached log file also..

log file.txt

[Bianca]

Hello,

This is causing the failing of the bitstream implementation:

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 7 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY 

This means that your XDC file is not configured according to your verilog code. Check if the nets have the same name or if the ports are not IOSTANDARD, correct the file.

best regards,

Bianca

[SAYALI]

I tried with this xdc file but I still facing bitstream error

XDC FILE.txt

counter.xise

log file.txt

[Bianca]

Hello Sayali,

Please see the following points:

• chose one designing tool and stick to it. If you still port your project from ISE to Vivado and vice-versa it's normally not to work
• I recommend you to stick to Vivado because it has more features and the webpack edition is free
• What you have sent me is a ISE project with an XDC file. ISE works with UCF, Vivado works with XDC
• If you want to sent the files, please send the source files not the project. (what you have sent is just the beginning of the project and I cannot reconstruct it without the source files)
• Synthesize your project again in Vivado. and see if your Errors persist. It looks there are just the ports that are different from your files to XDC file. 

If you still have errors, please attach the source files and the XDC if you decide to stick with Vivado or the UCF if you want to work in ISE or the whole project in an archive. 

 

Best regards,

Bianca