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Mahdi

All ADC channels are active on XADC demo!

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Hello,

I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue.

 

Best,

Mahdi

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Hi @Mahdi,

The verilog code below only handles to 2 switch cases. All other cases are considered default and set to selection 0.  You would need to alter the case statement to handle all 4 potential cases.   

always@(negedge ready)

case (sel)//next select is always next enabled channel, example: sel=0, sw=10 -> sel=1

0: sel <= (sw[1]) ? 1 : 0;

1: sel <= (sw[0]) ? 0 : 1;

default: sel <= 0;

endcase

thank you,

Jon

 

 

 

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Hi @jpeyron

Thanks for your response. I am aware that in this case the two switches are only connected to two channels. My goal is to get this to work with 3 channels eventually.

I did some experiments by feeding a 1 Hz, 400 mV sinusoidal signal with 0 V offset into three differential channels of Arty using a function generator and here are my observations.

When both switches are high, and signal is going through 1st differential channel (V_P and V_N pins), I see the LEDs blinking with 1 Hz frequency. If I connect the signal to the 2nd (A6-A7) and 3rd (A8-A9) differential channel, I observe the same response on LEDs.

If only one switch is active (SW1), then LD0 blinks no matter what channel the signal is plugged into. The same is true, when only SW0 is active. This is problematic, because I want to be able to plug in two independent differential signals at the same time.

 

Best,

Mahdi

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Hi @Mahdi,

My guess is that case statement needs to handle all four options explicitly to ensure that there is no unexpected results.  I will have bandwidth later this week to really dig into this HDL project. In the mean time another option is for you to port the Cora-Z7-10 xadc zynq/xadc wizard project here to the Arty-Z7-10.

thank you,

Jon

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Hi @jpeyron

Thanks for the suggestion. I managed to successfully use the Cora-Z7-10 project with Arty-Z7-10 board and did some tests by feeding a sinusoidal signal into different channels of ADC. Here are my observations:

This project uses the buttons to select active channels of ADC, so I started with having Vp-Vn active and monitored the voltage in SDK terminal. During this test, I observed similar voltage at SDK terminal compared to input terminal, and all of single ended pins (A0-A5) were inactive, except A3 which was showing about 30 mV. This means that even though A3 was not active during this test, there was still a signal reaching to Vp-Vn pins from A3. I am not sure if this would be due to a cross-talk issue, given that A3 is not located very close to those pins.

When a single ended channel was active (A0 to A5), no significant cross talk was observed which confirms that single ended channels are working properly, except A3.

I also did this test for three differential channels (A6-A7, A8-A9 and A10-A11) and realized that cross talk is even higher for these channels, in a way that A8-A9 was working properly while it was active, but it was also reading about 0.3 V from Vp-Vn and 15 mV from A6-A7 and A10-A11 channels. The same scenario was true for other differential channels with smaller cross-talk values. This board should not clearly act like this, unless something is physically wrong with the channel sequencer. I hope these observations help you, whenever you have the chance to work on it.

Regards,

Mahdi

Edited by Mahdi

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