Analog Discovery 2 Waveform Sampling Rate for log analyzer

[Khoi Ly]

Hi Digilent,

I have two questions that i would like to ask about the logic analyzer function on the Analog Discovery 2. 

1. With the rating of 100Mhz logic analyzing sampling rate, what is the maximum frequency can I capture? What about the spi frequency of 20Mhz?

2. The waveform limits my number of samples to 4096 (right above the rate settings). This link shows that waveform software allows 16384 samples. or even 10000000 samples

https://forum.digilentinc.com/topic/9043-capturing-both-uart-and-spi-data-on-analog-discovery-2/

How do I fix this?

 

Thanks

 

Khoi Ly

[jpeyron]

Hi @Khoi Ly,

I moved this thread to the scope and instruments section where more experience AD2/Waveforms engineers look. 

thank you,

Jon

[attila]

Hi @Khoi Ly

Use the record mode to capture more data than the device buffer at a maximum rate of about 1MHz.

[Khoi Ly]

Thank you very much for your reply. I will try it out today. In the mean time, I wonder if you could help me with this

 

 SCLK        - pin 13 (SCK)
    DIN         - pin 11 (MOSI)
    DOUT        - pin 12 (MISO)
    DRDY        - pin 9
    CS          - pin 10 (CS)
    RESET       - pin 8 (or tie HIGH?)

On the Waveform software, when I select add SPI in Logic Analyzer I would assume the following:

Select  = CS pin (DIO3 in my case)

Clock = SCLK pin (DIO0 in my case)

What should the data be? Doen't data need two wires one is MOSI the other is MISO?

I also have data ready pin, so I will create a separate channel for it, right?

Khoi Ly 

[JColvin]

Hi @Khoi Ly,

If you are wanting to view both the MOSI and MISO data lines, it is my understanding that you will need to create two separate SPI channels in the logic analyzers, with the data set to MOSI and the other set to MISO. If you have a separate data ready pin, you would want to create a separate input for it; you can then have the logic analyzer acquistion be triggered off of it whether you choose to attach the data ready pin to one of the external triggers or be one of the digital inputs.

I don't know what device you are interacting with so I can't speak much towards the reset, but presuming it is a active low reset for the external device I would probably tie the pin to a logic high state/use a pull-up resistor.

Thanks,
JColvin

[Khoi Ly]

Hi, I have setup the SPI logic analyzer for the SPI communication between arduino and TI ADS 1256.

I place a digital pin from arduino called DIO7 that triggers right before the microcontroller receiving ADC data from the ADS 1256 (DIO7 Falling edge trigger on the logic analyzer). The CS pin is kept LOW the entire time

digitalWrite(7,HIGH);

....

digitalWrite(7,LOW);
adc_val = SPI.transfer(0);
adc_val <<= 8; //shift to left
adc_val |= SPI.transfer(0);
adc_val <<= 8;
adc_val |= SPI.transfer(0);

I would like to fully understand the interpretation of the logic analyzer results in the waveform software shown in the link below

https://drive.google.com/file/d/1ieTI4vWpnWssZHj98EXpZpL0A1r04CdD/view

We know that the Data line (MISO) should only be triggered from the first rising edge of the clock. But the logic analyzer interprets the data as if the data line (MISO) from this logic analyzer appears to pulse before the clock. I also use oscilloscope to probe the timing between the clock and the data line and it matches with the signal pulses on the logic analyzer, but why the logic analyzer interpret the data as follow?

The first 8 bits are B01111111 ------ The only way that we get a 0 bit in the first spi.transfer is if we begin counting the data line (MISO) before the clock goes HIGH

The second 8 bits are B11111111 -------- It is a bit hard to see, so I ignore this one

The third 8 bits are B10111001 ------ Similarly, the ending bit of the last spi.transfer is 1, but you can see that it is one clock cycle before the last clock pulse

The setup is Active LOW, Sample RISING,First MSB, format BINARY, no leading or trailing, start at 0 s.

When I set the Data line to be MOSI It works correctly for this line of code: SPI.transfer(0xFE); //0b11111110

 

 

[attila]

Hi @Khoi Ly

Your SPI signal is active on rising edge, data bit changes on rising clock edge, so use in the Logic Analyzer sample on falling edge to interpret it correctly.