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Audrius

Zybo Z7 serial port does not output "Hello world" message when it does output "Zybo Z7-20 Rev. B Demo Image"

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Posted (edited)

When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages:

Connected to /dev/ttyUSB1 at 115200
Initializing...
init:done
Zybo Z7-20 Rev. B Demo Image

This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working.

The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect.

I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly.

I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0)  at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior.

I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears.

I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7).

I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux)

I attach SDK logs and synthesis logs. Board files I have downloaded from https://github.com/Digilent/vivado-boards/archive/master.zip. After installing as described in https://reference.digilentinc.com/vivado/installing-vivado/start  I was able to find and select the Zybo Z7 - 20 after restarting Vivado.

While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes.

Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful.

Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. 

 

 

 

sdk.log

synthesis.log

Edited by Audrius
Added Zybo z7020 tag

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15 answers to this question

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Hi @Audrius,

Please run my verified hello world project here since you are able to get USB UART communication through the OOB Demo but not through your hello world project. Make sure that you have correctly installed the Digilent Board files as described here.  Were you able to see information in the serial emulator when you press a button? Does the switches turn on the corresponding LED? I have attached some screen shot of my project and the tera term output. Once you have launched SDK with this Vivado 2018.3 Zybo-Z7-20 project program the fpga and then right click on the application and select run as->Launch on hardware(system debugger). Make sure the mode Jumper JP5 is set to JTAG.

cheers,

Jon 

Zybo_Z7_hello_world_2018_3_2.jpg

Zybo_Z7_hello_world_2018_3_1.jpg

Zybo_Z7_hello_world_2018_3.jpg

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Hi @Audrius,

In linux the cable drivers need to be installed manually.  Here is an Xilinx AR that discusses this. Also install Adept 2 here and run djtgcfg enum in the command line.  Please attach the terminal text response to the djtgcfg enum command.

thank you,

Jon

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Posted (edited)
$ djtgcfg enum 
Found 1 device(s)

Device: ZYBO-Z7
    Product Name:   Digilent Zybo Z7
    User Name:      ZYBO-Z7
    Serial Number:  210351A786B0

$ dadutil showinfo -d ZYBO-Z7
Product Name:           Digilent Zybo Z7
User Name:              ZYBO-Z7
Serial Number:          210351A786B0
Product ID:             01D00257
Firmware Version:       010A
Device Transport Type:  00020001 (USB)
Device Capabilities:    00000001
    DJTG - JTAG scan chain access

Thanks for your care.

Ok I have installed Adept 2, here is the output on the command you asked and also another that may be useful. I think I have already installed the drivers before but anyway I have verified everything again step by step, the log is attached. I have freshly exported hardware from Vivado to make sure the code in SDK has no any of my alterations.

Unfortunately there is not so far any difference in behavior.

I also tried to use minicom instead of SDK window. After attempting to run the hello world example, it prints the same "Demo Image" phrase:

$minicom -b 115200 -D /dev/ttyUSB2

Welcome to minicom 2.7

OPTIONS: I18n 
Compiled on Nov 15 2018, 20:18:47.
Port /dev/ttyUSB2, 18:33:41

Press CTRL-A Z for help on special keys

Initializing...
init:done
Zybo Z7-20 Rev. B Demo Image

(if JP5 is in the middle position). If on "JTAG", no output.

drivers.log

Edited by Audrius

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Great, it now worked!

Well, initially the SDK was showing me the messages about some wrong executable selected for download (attached). However then I have removed the folder GSWZ_2018_3_ZYBO_Z7_20.sdk, repeated all steps of creating the bitstream in Vivado starting from synthesis and exported hardware again, it unexpectedly worked, showing "Hello world" on the tty output as if nothing. It even works with JP5 in the middle QSP1 position. I also was able to get the "Hello world" easily on TFC Debug virtual terminal. 

I did not change anything in my board files or system configuration. Also, yesterday evening I brought Zybo Z7 to my Windows 7 workstation and repeated all steps there, reproducing essentially the same behavior. Probably Vivado 2018.3 cannot create a working "Base Zynq" project for Zybo Z7 from scratch, even with the board files provided. However now I can use your reference project as a starting point, by adding my AXI modules there.

Thanks a lot for your help. May the Force we with you!

executables_w.png

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Hi @Audrius,

I'm glad you were able to get the project working! I made the project based an older getting started with ZYNQ tutorial for the Zybo here. You should be able to create your own project following this tutorial as well. I would also suggest making sure you have the digilent board files installed correctly as shown in this tutorial here.

cheers,

Jon

 

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Posted (edited)

Hello! @jpeyron

Dir "jpeyron" there is a picture in your answer of  block design for Zynq ("hello world" generate example). But you wrote, that you used vivado 2018.3.
 I use vivado 2017.4, when i connect block like in your picture and start "implementation" - all be ok. When start "generate bit stream" - i get error.
Could you give more pictures that explain how to edit properties of each blocks of that (Zynq core, AXI interconnect, GPIO, proc reset) ???

Edited by andre19

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Hi @andre19,

Welcome to the Digilent Forums. 

What ZYNQ development board do you have?

I would suggest following the Getting Started with Zynq tutorial along with making sure that you have the Digilent board files installed.

Digilent has board files that correctly configures the ZYNQ processor along with the DDR3. Here are the tutorials that we have available Getting Started with the Vivado IP IntegratorGetting Started with VivadoInstalling Vivado and Digilent Board Files and Getting Started with Digilent Pmod IPs.  I will pass on your desire for more information on the Zynq core, AXI interconnect, GPIO, proc reset IP Cores to our content team although I believe that currently we do not have the bandwidth to create tutorials for how to edit properties of the Zynq core, AXI interconnect, GPIO and the process reset IP Cores.

I would suggest looking through the Zynq-7000 SoC Technical Reference ManualAXI Interconnect v2.1 LogiCORE IP Product GuideProcessor System Reset Module v5.0 LogiCORE IP Product Guide and AXI GPIO v2.0 LogiCORE IP Product Guide. Xilinx does have a lot of documentation/examples on how to use their IP Cores available from the block design by right clicking on the IP.

I would also suggest looking here (if you used the default installation path): " C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers" for examples on how to uses their IP Cores in SDK. The ZYNQ book is also a good source of information as well.

If you are still having issues with the Getting Started with Zynq tutorial please attach screen shots of your block design.

best regards,

Jon

 

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Hi @jpeyron

Early i have worked with arty A7 board and programmed it via Vivado.
Now i have get another board with Zynq 7020 and i start to write code in vivado - it is not Digilent board (its is very bad(( and hard to start for me ) .
I choose my chip in vivado and combinated IP blocks. I want at first step to make transmitting "Hello world" to PC. But, after generating bitstream i have get errors, i  don't understand hove to fix tham((

Best regards

block diagram.jpg

my errors.jpg

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Hi @andre19,

We provide board files for our boards to assist with constraining some of the components like the USB UART bridge as well as the DDR. You need to use a xdc file to constrain the UART_O_0_rxd and the UART_O_0_txd signals to specific pins on your development board.

Does the manufacture provide a board file or XDC for you to use? 

I would also suggest reaching out and or looking through your ZYNQ development board's manufacture's  provided documentation/resources to  see what resources they provide.

best regards,

Jon

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Hi @andre19,

I would suggest looking at the schematic here for the pins that you will need to use in your XDC. This here might be the E310 XDC. I would suggest reaching out to ettus about resources for their board.

best regards,

Jon

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Dear @jpeyron

Could you help me and create simple project for transmit to PC from chip "Hello world"  (i will downloaded them and probe to program my chip . . .)?

It will be my first point of teaching to program Zynq. I looked at information about pins, but confused with working with them((

Best regards.

 

 

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Hi @andre19,

There is a few thing that must be done to send data through the UART with a ZYNQ processor.  Unfortunately we do not have the bandwidth or your development board to create a completed UART project for this board.

This is my understanding of the general tasks that need to be accomplished: 

1) You will need to correctly configure the ZYNQ processor. I would look at the  Zynq-7000 SoC Technical Reference Manual. You can also look at our ZYNQ development board's board files and schematics as a reference. 

2) You will need to constrain the output/input signals using an XDC or through a board file.   

 

best regards,

Jon

 

 

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Hi @jpeyron
I have used your information - it has some helped me.
Thanks!)
1) I have connected .XDC file  (to constarints)  https://github.com/OrionInnov/uhd-fpga/blob/master/usrp3/top/e300/e310.xdc?_ga=2.195350511.234626281.1558874700-227237821.1553275560
2) i have Created blocks like in youtube example ( 

and  Generate succesful bitstream.
Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image.
SDK don't see FPGA (((
(I give rar of my project HLS + SDK   https://m.mega.dp.ua/kMWSx)
What do you phink about connecting to FPGA?
Best regards

block design.jpg

board identification.jpg

Problem in program FPGA.jpg

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Hi @andre19,

1) Its my understanding that you would not need to use the axi uart lite but rather the uart pins off of the ZYNQ processor.

2) Does your board have different mode settings. If so make sure that the mode is set to JTAG.

best regards,

Jon

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