Memory Block Generator - data access

[donwazonesko]

Hello!

I've created memory block using ip catalog that keep the data received from FFT in vivado, and now i want to access the data. I know that i need to increase the address but I'm not sure exactly how i am suppose to do it. Could you please recommend me something?

Here's my code memory block with address incrementation:

COMPONENT fft_mem_1024_32bit
  PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;

Memory_fft_mem32_1: fft_mem_1024_32bit
        PORT MAP (
          clka => dclk_in,
          ena => '1',
          wea => FFT_MEM_VALID_1,
          addra => adres_RAM_1,
          dina => FFT_MEM_1,
          douta => MEM_DATA_OUT_1
);

  Adresowanie_Pamieci_1: process(dclk_in)
  begin
    if(dclk_in'event and dclk_in = '1') then
      if(FFT_MEM_VALID_1 = "1") then       
          adres_RAM_1 <= std_logic_vector(unsigned(adres_RAM_1) + 1);
              if (adres_RAM_1 > X"3FF") then
                  adres_RAM_1 <= "0000000000";
              end if;
      end if;
    end if;
  end process;

 

[jpeyron]

Hi @donwazonesko,

BRAM is basically an array of arrays. In VHDL it will look something like this  : ""type BRAM is array (0 to 2**AddrBits - 1) of std_logic_vector(RAM_Width-1 downto 0);" where AddrBits and  RAM_Width are constants that defines the size of your  BRAM.

The process of reading and write are done "simultaneous" into an single process. Something like this :
 

       ram_process: process (clk)
       begin
          if Rising_Edge(clk) then
             if (We = '1') then                   -- when you want to write into you BRAM.  
                BRAM(Addr) <= data_in; -- you store the input data on a given address.
             end if;
           data_out <= BRAM(Addr);    -- after writing, you output your data.
          end if;
       end process ram_process;

Here is the Nexys 4 DDR Spectral Sources Demo which should be helpful with the FFT part of your project.

thank you,

Jon

 

 

 

[donwazonesko]

dear @jpeyron I've change the type of ram to "Simple Dual Port RAM".

 

Here is the entity for this ip core:

entity fft_mem_1024_32bit is
  Port ( 
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );

I think using this is better than single port. Could you please tell me how do i change the enb status once the memory is full(32 bits x 1024 elements)? 

 

Best Regards,

Michael