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why do i get this error every time i change my vhdl code ?


hello I am used to work on the ALTERA DE2 board using queartos , now i have the ZEDBOARD of xlinx . everytime i press the  "RUN Synthesis " I get the following error   


There are no HDL sources in file set 'sources_1'.
Please use the Add Sources command.


 how to fix this problem ? 


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Hi @tom_123,

Welcome to the forums. It appears that your VHDL source file is not being recognized as the top file. . Are you able to right click on the source and set it as the top file? Attach a screen shot of what is available for you when you right click on your VHDL file. Please attach the VHDL code and xdc file you are using. Here is the Zedboard resource center.  Here is a Verilog project for the Zedboard. I would also suggest to install the digilent board files.

thank you,


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