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ababa

Nexys 4 DDR (Microblaze based model; vivado doesn't generate bitstream file to this board)

Question

Hi;

I'm trying to make a Microblaze based embedded microprocessor using Nexys 4 DDR and Vivado 2018.3.

For the same model, Vivado generates Bitstream file for another board (Artix 7 AC701 evaluation form) but for my board (NEXYS 4 DDR) Vivado doesn't generate the bitstream file. 

May I find any logic reason ?? 

Even though I have included the board "NEXYS 4 DDR"  in the list of board_files inside Vivado. But in any case, it doesn't work!

Thanks

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Hi @ababa,

Welcome to the forums. When Xilinx releases a new version of Vivado it can have unforeseen issues and Vivado 2018.3 was just recently releases. Please attach screen shots of the errors, block design and wrapper file.  What type of project are you trying to create?  Did you follow the digilent board files tutorial here? I followed an older microblaze tutorial for the Nexys 4 DDR here without issues.  Here is a completed hello world microblaze project. When using this attached project make sure that you have installed the digilent board files.  The only issue with Vivado 2018.3 and our content I am aware of is discussed in this forum here. Here is our resource center for the Nexys 4 DDR as well.

cheers,

Jon

Nexys4ddr_hello_work_2018_3.jpg

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Thanks for your valuable answer;

For the complete project "hello_world", may you give me the link to its tutorial? This design works well without any problem. While the tutorial you have cited in your answer doesn't give the same final design; but it generates an error message that appears later  "MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its Bus Interfaces are connected properly UNABLE to STOP MicroBlaze". 

Thanks 

 

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Hi @ababa,

I believe you do need to set the reset type in the clocking wizard to Active Low as discussed in 4.4 of the tutorial linked above as well as being linked here.

thank you,

Jon

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Hi @ababa,

Please attach a screen shot and a path of where you added the board files along with a screen shot of the contents of the board files. My path would be "C:\Xilinx\Vivado\2018.3\data\boards\board_files".  Please attach a screen shot of your block design and your wrapper file.  Did you select the Nexys 4 DDR when creating your project? Could you attach a screen shot of the error. Are you getting this error in Vivado or in SDK?  Is the Mode Jumper set to JTAG. 

thank you,

Jon

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