How to read data from PL section of Zybo written in BRAM

[Sami Malik]

Hi,
I have made the block diagram of BRAM and populate it from PS section of Zybo. I have made the PORTB of BRAM as external. Now I want to read this BRAM from PL section but I don't know how to read it using verilog code. 
Do I have to make changes in design_wrapper.v of my block diagram and then I have to do some instantiation in my main.v or there is any other method to do so? 

Regards,

Sami

[jpeyron]

Hi @Sami Malik,

Here is a link for using Block Ram in Verilog with Vivado. I have used IP Cores with a verilog top file like in the Zybo XADC demo. If you are also using the zynq processor then i believe you would need to use the IP Core along with controlling it from a SDK application.

thank you,

Jon

 

[Sami Malik]

Block diagram of what I have done so far is given below. I don't know whether its correct or not. Please correct me if I am wrong. 

[jpeyron]

Hi @Sami Malik,

Here is the Block Memory Generator v8.3 LogiCORE IP Product Guide. Here is a xilinx forum thread that might be helpful. Could you be more specific about what you are trying to do?

thank you,

Jon

[Sami Malik]

Thank you sir,

I have checked the manual and thread. But sir I want to read and write to BRAM using verilog how can I achieve it? 

Is there any way to make an array whose starting address in memory will be same as the starting address of BRAM(0x4000000)? Basically in this way I think I will be accessing the BRAM.

Another thing is that can I assign values to componants directly in hdl_wrapper.v file of my block diagram? I was trying to do so but it failed in generation of bit stream. I was doing this thing for the same reason that is to write and read data of BRAM using verilog...