Arty: Selectable 2.5V I/O bank(s) for LVDS

[Scott Gilbertson]

Digilent, if you're planning to make a new revision of the Arty, please consider allowing LVDS_25 for high-speed differential output. The Artix 7 doesn't have an "LVDS_33" I/O option, so you need a 2.5V I/O bank if you want LVDS output. As far as I can tell all the I/O banks on the Arty are hardwired to 3.3V, so you can read, say, FPD-Link LVDS data, but you can't drive an LVDS display without an external driver chip, and that means sending hundreds-of-MHz single-ended signals to the driver.

I think the ports in question would be those on the JB & JC connectors, because those are the two high-speed PMOD ports. A jumper to switch those to 2.5V would be great. Maybe some of the Arduino & ChipKit pins too.

[sbobrowicz]

Hi Scott, welcome to the forum.

Thanks for the feedback, we agree that adding an option to power the high-speed pmod signal lines at a lower voltage would be a good feature add. Unfortunately, implementing it on Arty would take a significant reorganization of the layout and FPGA bank connections for several onboard devices. This means it is not likely to be designed into a future rev, where we typically only make changes for fixes and minor-tweaks. We will certainly consider it on future boards though.

On the Arty pmods, one thing you could consider trying for high-speed differential output is to use the TMDS_33 IOSTANDARD. TMDS is a current-mode logic (CML) interface that we use for driving our HDMI input and output ports. This document http://www.ti.com/lit/an/scaa062/scaa062.pdf explains how you could get away with connecting a CML output (such as TMDS_33) to an LVDS input, assuming the LVDS device can support a common-mode range up to 3.3V. 

 

[jcv65]

HI,

I have a situation in which I have to interface my ARTY with an ADC evaluation board that uses only LVDS (2 inputs, 2 outputs).  In the message above you mention that one could use for High-Speed differential Output the  TMDS_33 IOSTANDARD.  Is this a setting I have to specify in my Vivado project?

 

Thanks

[jcv65]

Hi Sbobrowicz,

Do you think that another option to solve this LVDS voltage configurability issue may be to move from the ARTY to the NEXYS VIDEO ARTIX-7 FPGA-trainer board...This board seems to have selectability for the port banks' voltage...

Thanks

[JColvin]

Hi jcv65,

I have forwarded this question on to some of our applications engineers who will get back to you here on the forum.

Thanks,
JColvin

[JColvin]

Hi jcv65,

The changing of the I/O Standard to the TMDS_33 IOSTANDARD can be done in the XDC file for the Arty.

Thanks,
JColvin 

[sbobrowicz]

Hi jcv65,

Tried to post this earlier in response to your first post, but the forum was down...

You have to specify the IOSTANDARD in your XDC file. You can start with the Arty Master XDC we provide (which specifies the IOSTANDARD for the pmods as LVCMOS33) and change the IOSTANDARD for the signals you want to use to TMDS_33.

I've never actually tried this before, but it seems like it should work. If you keep us posted on whether or not this works it would be very helpful for us and the community :).

Edit for clarification: I've never tried using the TMDS_33 IOSTANDARD to drive LVDS inputs via the external circuit I linked to previously. I have, of course, tried changing the IOSTANDARD in an XDC file before, despite what I implied above  

Regarding the Nexys Video, yes that would be a cleaner solution I'm sure. You can set the adjustable voltage at 1.8V and then just use the LVDS IOSTANDARD for both inputs and outputs. For the connection, you will either need to use the JXADC pmod connector or the FMC connector with a breakout board. The JXADC pmod would be the far more convenient method, but peak at the schematic and make sure the 100Ohm resistors between the FPGA and the pmod connector won't cause any problems (note the capacitors are not loaded). You could always shunt them if need be. 

 

[jcv65]

Hi Sbobrowicz,

I understand that the PMOD connectors may not be high speed (due to their impedance).  Do you know of any other connector I could adapt to my Arty to make it high speed?  I need to run signals at about 100MHz... Hopefully I can include a circuit to make the translation from TMDS_33 to LVDS 2.5V

Thanks

[Scott Gilbertson]

21 minutes ago, jcv65 said:

I understand that the PMOD connectors may not be high speed (due to their impedance).  Do you know of any other connector I could adapt to my Arty to make it high speed?  I need to run signals at about 100MHz... Hopefully I can include a circuit to make the translation from TMDS_33 to LVDS 2.5V

That much I've figured out. JB and JC on the Arty are high-speed (no series resistors). I had no problems running 280MHz single-ended LVCMOS33 from JB to an LVDS driver chip.  See section 10.2 High-Speed Pmod, here: https://reference.digilentinc.com/arty:refmanual

You can also use the Arduino/ChipKIT shield connectors. You can get an XDC file here: https://reference.digilentinc.com/arty. Un-comment the connectors you're using. You can often remove the IO standard definitions from the XDC, and let Vivado figure it out. If you use a SelectIO Interface Wizard, for example, it lets you pick which differential signaling standard to use.

If you're only using part of, say, the shield connectors, I've found what works well is to write a custom VHDL/Verilog wrapper, outside the generated block-diagram wrapper, just to adapt the block diagram interface names to the actual pin names. That way you don't have to mess with the XDC file every time you change some little thing in the I/O definitions.

[sbobrowicz]

I'd recommend using either JB or JC as Scott suggested. You should be able to get the fasted speeds off of those pins (faster than the shield), and the traces are routed as differential pairs. 

[Elvi]

I am trying to use sdk c code and gpio pmod to read lvds signal. Is this practical? 

[D@n]

No.

Dan

[zygot]

On 4/18/2016 at 5:42 PM, Scott Gilbertson said:

That much I've figured out. JB and JC on the Arty are high-speed (no series resistors). I had no problems running 280MHz single-ended LVCMOS33 from JB to an LVDS driver chip.

It is certainly possible to hook up an LVDS driver to a differential PMOD using an interface board of your own creation. Driving multiple single-ended outputs simultaneously have their own issues to take care of, and you have to be aware of signal integrity details. The larger problem with the Digilent differential PMOD connectors for most of the boards is related to clocking and timing. Without differential clock inputs and clock outputs most applications become very complicated. Series resistors are not necessarily an impediment to an ability to toggle an FPGA output. They do represent a termination scheme however and that has implications about how you might implement an IOSTANDARD using the termination specified by Xilinx ( or any FPGA vendor ) for a given standard. The analysis might be  more complicated than you are aware of. Unfortunately, most LVDS driver  and particularly receiver ICs are quite limited relative to the native performance of Series 7 FPGA IO. I've looked. If you know of any above 500 MHz or so please let me know. With some effort you can also convert the FPGA IO to PECL or ECL but I'm not sure that anyone sells that stuff any longer.

The best solution for work needing a robust differential interface is to find a vendor selling an FPGA board with a well designed differential interface. Sadly, that is not Digilent. Their Zedboard, Nexys Video, and Genesys2 do have FMC connectors that ought to provide everything that one needs but designing you own FMC board is not a trivial or inexpensive undertaking. If you pursue that approach do check the schematic to very that the IO pins are differential pairs. I have not verified that differential IO on any of those boards are actually laid out as differential pairs to the connector; and thy must be.

[BrentMoch]

I second this request. LVDS is very common and it's a shame the board doesn't support it.

One other request I have is to provide for termination resistor pads on the board, close to the Artix part. Xilinx claims to let you use LVDS inputs (no outputs) with a higher VCCO, so in that case we could use LVDS_25 inputs with the JB and JC connectors using a 3.3V VCCO. The one caveat, though, is that you cannot use the built-in 100-ohm termination when doing this, so we'd have to put the termination resistors external to the part. If there were pads on the board for this that would at least let us use LVDS inputs.

-Thanks