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Hi @Ahmed Alfadhel,

In general, the Digilent IP cores are altered versions of the following xilinx IP's cores: AXI UART Lite AXI Quad SPIAXI GPIO and  AXI IIC.  We made generic IP cores that work with our pmod port using the Pmod_Bridge and the contents in the if folder of the vivado library.  Digilent pmods use different amounts of pins.  So to be able to handle multiple communication types as well as different number of pins the Digilent IP cores have the ability to connect to all 8 I/O pins. They are numbered to match the pins on the ports so as you may have noticed there is no pin 5 or pin 6 since they are vdd and gnd. There is a input, output and a T connection available on the pmod out connection for each available I/O pin. If you are wanting to free up the lower pins on the pmod port(JA,JB,JC..) while using the generic PmodDA3 then right click on the pmod out of the generic PmodDA3 IP core and select "make external". In this situation you will need to constrain the pins using an xdc.  

thank you,


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