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Can I use XADC to sample the input signals?


I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module.


Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board?


Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board?



Shruthi Sampathkumar.

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Hi Shruthi,

I'm not sure if anybody at Digilent has done much with the HDL Coder from Matlab, but after doing a bit of research on my own, it seems you can either use the HDL Coder within Xilinx tools (for which you would need the Vivado System Generator), or if you have already generated the Verilog code, you could just use the normal Vivado Design Suite to implement your code onto the FPGA. So yes, I think you can just use the Vivado Design Suite and XADC.

Again, I personally haven't used the HDL Coder, so more detailed questions would need to be addressed to MathWorks.


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