Error building OOB Design in ISE 14.4

[bent9]

Hi

I am trying to build the out-of-box design myself, so I can modify it.

I tried to follow this guide, but cannot generate the bitstream using xilinx platform studio that came with ISE 14.4 (The version that was used in the guide). I get the following Error when generating the bitstream the Design, without making any changes:

 

Failed to run core generator for <system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1> macro.

 

I cannot figure out why. Does anybody have an Idea what to do?

 

I would much rather use Vivado, has somebody ported the out-of-box project so that it can be built with Vivado?

I am very inexperienced with Vivado as well, is there any easy way to replicate the project so I can use it with the digilent linux kernel?

Thank you!

[jpeyron]

Hi @bent9,

Welcome to the forums! What development board and OOB project are you referring to?

thank you,

Jon

[bent9]

18 hours ago, jpeyron said:

Hi @bent9,

Welcome to the forums! What development board and OOB project are you referring to?

thank you,

Jon

How could I forget to include that info...
I am working on the Zedboard (rev D) and the OOB project here. That zip includes the sd card image that is preloaded onto the sd card that is shipped with the zedboard.
I managed to build my own linux kernel from the digilent sources, but I would now like to generate my own bitstream to use the PL of the zynq chip and thats where I am stuck with the errors.

Thanks for your help.

[jpeyron]

Hi @bent9,

I do not have much experience with XPS.  So I would not be very helpful with this topic. If possible I would suggest using Vivado/SDK and Petalinux. Here is a forum thread that discusses using petalinux with the zedboard that should be helpful. 

Jon